Hello, I've been working on a Multistage amplifier circuit for the past couple days and I cant seem to get it working correctly. The specs that I need to design for are:

a. Input impedance = 200 kΩ
b. Output impedance = 200 Ω
c. AC voltage gain = 300
d. Low frequency -3 dB point = 50 Hz
e. High frequency -3 dB point = 100 kHz
f. Output voltage swing = 6 V peak-to-peak without distortion
The output load resistor is 1 kΩ. The dc power supply is no higher than 20 V. There should be no operational amplifier in the circuit.

I've attached my schematic, as well as the output and frequency response for my circuit.

My capacitor values are off because my high and low frequency cutoffs aren't showing up, but I'm not sure which equations and values I should use to fix it.

My main request is if anyone has time, would you glance over the circuit and see if it looks like it would work and makes sense. If not, tell me which part i should mess around with more.

Thank you

 

Did you have a particular reason for placing a 10 microfarad (C17) to ground on the output of you amplifier?

hgmjr

 

I wonder if taking the output through the 10 mikes might not help. A quickie run on the calculator shows Xc = about 16 ohms.

 

I had built the circuit, then my dad's friend had built this one this way. Here's the paper he had given me:

 

Another problem I see is you have the requirement that your input impedance be 200K. However you have put a 100K on your input to ground. That needs to be corrected if you are to meet the intended input impedance.

hgmjr

 

ok, I overlooked that. I changed that resistor value from the Gate of the JFET to ground to 220k

 

Some of the resistor values are odd - you should decide (and state) if they are 5% or 1% tolerance. You can get 200K in 1%. But 500 ohms only comes in potentiometers.

 

Another thing to look at is the fact that you are seriously overdriving your amplifier. If you are expecting a gain of 300 and an output of 6 Volts peak-to- peak, then you need to use an input signal that is 1/300th of the expected output. In this case that would be around 20 millivolts peak-to-peak.

hgmjr

 

ok, I overlooked that. I changed that resistor value from the Gate of the JFET to ground to 220k

That is more in keeping with the specifications given.

hgmjr

 

Actually, now that I look at the input, you are going to need to use another resistor to the positive supply to bias the gate. You have a single ended supply not a dual supply.

hgmjr

 

Actually, now that I look at the input, you are going to need to use another resistor to the positive supply to bias the gate. You have a single ended supply not a dual supply.

hgmjr

I'm not too sure what that means to be honest, do you mean i have to put another resistor after my DC voltage source?

 

Looking at the sketch provided by your Dad's friend, you can see what beenthere was talking about earlier. The 10 microfarad capacitor is actually the output dc-blocking capacitor through which the output passes on the way to the load.

hgmjr

 

Isn't C15 on the wrong side of R23? And C16 being 200 uF will probably cause so much phase shift that the amp will motorboat. It's also less than 1 ohm at 1 KHz.

 

I'm not too sure what that means to be honest, do you mean i have to put another resistor after my DC voltage source?

What I was referring to is the need for a resistor from the gate of the junction fet to +15. If you notice, you have the gate and the source at more or less the same potential. Without a slightly greater DC bias voltage on the gate than the source, I don't think you will be operating the FET in its linear range.

hgmjr

 

Isn't C15 on the wrong side of R23? And C16 being 200 uF will probably cause so much phase shift that the amp will motorboat. It's also less than 1 ohm at 1 KHz.

Beenthere, Are you thinking that the output stage was intended to be a common emitter and not a common collector stage?

hgmjr

 

Thank you all for your input. I'm going to use your suggestions and try to fix it up a bit, I'll post back in here with an updated version if you all would check back tomorrow at some point

Thank you again

 

I was looking at things individually that didn't "look" right... But yes, I just realized that taking the signal off the emitter makes the gain less than 1. For a low fixed frequency, it might be reasonable to make the circuit work with a DC input, and then make tweaks after adding the coupling caps. 1 KHz isn't a strain.

 

I may have been a bit hasty in my recommendation to add some positive bias to the gate of the JFET. The Vgs minimum is -0.5 volts and so it looks like those conditions are being met without the need for another resistor on the JFET's gate.

hgmjr

 

Well, I'm getting a reasonable peak-to-peak output and my only trouble is figuring out which capacitors to change to influence the -3db frequencies. I know that the lower frequency is influenced by the bypass capacitor and coupling capacitor, but when i change those it doesn't seem to do anything

Do you guys know of any equations that I could use to make it easier, rather than simply guessing and checking? My book does not really give many equations, and it's hard to find them online.

 

I think you will need to disconnect the grounded end of the 10 microfarad capacitor on the output and add a 1K resistor from the open end of that cap to ground. Then take your output from the junction of this added 1K resistor and the capacitor. This will satisfy the 1K load that your spec requires you to drive.

hgmjr