Pi Generator

Thread Starter

BR-549

Joined Sep 22, 2013
4,928
I wasn't sure where to post this. The circuit I need is to study resonance, but it will probably require a digital solution.

I have a ac signal generator that outputs 300 millivolts from 60 cycles to 150 megacycles.

I need a circuit that will half wave rectify this signal........and allow me to select from 1 to 12 half wave output alternations.

I need a complete, symmetrical output of 1 to 12 half-wave positive pi. One to twelve humps.

A proof of concept, one low frequency concept circuit, will suffice.

Any and all strategies, concepts or alternatives are welcome.
 

EM Fields

Joined Jun 8, 2016
583
I wasn't sure where to post this. The circuit I need is to study resonance, but it will probably require a digital solution.

I have a ac signal generator that outputs 300 millivolts from 60 cycles to 150 megacycles.

I need a circuit that will half wave rectify this signal........and allow me to select from 1 to 12 half wave output alternations.

I need a complete, symmetrical output of 1 to 12 half-wave positive pi. One to twelve humps.

A proof of concept, one low frequency concept circuit, will suffice.

Any and all strategies, concepts or alternatives are welcome.

Half-sine burst generator.png

This is operating at 1kHz. Do you need a circuit description?
 

Thread Starter

BR-549

Joined Sep 22, 2013
4,928
OK.....of the several U2 data sheets I downloaded....which concentrated on the flip flops.....I have no idea of what the bottom of U2 does.

I can not see the connections and function of SW1.

What is V3?

Is C1 discharged by R2?

I believe that U1 is converting the positive pi input into a positive square. This is used to latch U4 and inverted thru U3 and applied to clock input of U2.

I have no idea of what U2 does.

U8, U5, U6, and U7 sync the second latch of U4. But not sure how.

So please clear up SW1 and V3. And C1.

And then kindly explain circuit operation.
 

Thread Starter

BR-549

Joined Sep 22, 2013
4,928
EM.....I'm assuming you used a simulator. I have never used one. Before you explain the circuit.....are you able to sync circuit signals to the input?

If so....may I see the signal at inputs of U4, LBAR, CTEN and C1?

Thanks.
 

EM Fields

Joined Jun 8, 2016
583
Half-sine burst generator3.png Half-sine burst generator3 plot.png
OK.....of the several U2 data sheets I downloaded....which concentrated on the flip flops.....I have no idea of what the bottom of U2 does.

I can not see the connections and function of SW1.

What is V3?

Is C1 discharged by R2?

I believe that U1 is converting the positive pi input into a positive square. This is used to latch U4 and inverted thru U3 and applied to clock input of U2.

I have no idea of what U2 does.

U8, U5, U6, and U7 sync the second latch of U4. But not sure how.

So please clear up SW1 and V3. And C1.

And then kindly explain circuit operation.
There was a technical error in the circuit, which I've fixed, and the circuit now looks like this:

Half-sine burst generator3.png
Part of the plot looks like this:
Half-sine burst generator3 plot.png
Which shows the AC input signal, the clock derived from the input signal, the load pulse, and the 12 half-sine burst output pulses. U6 is a 4 bit binary down counter and is used to determine the number of output pulses in a single burst.
How it works is that the number of output pulses desired is placed on U6's data inputs, then when V3 loads that number into the counter by momentarily pulling LOAD low, the counter will decrement and a half-sine output pulse will be generated for every clock cycle until U6 counts down to zero. When that happens, the counter will be disabled and the outputting of half-sine pulses will cease until the next time V3 goes low.

CIRCUIT DESCRIPTION:

V2 is a continuous sinusoidal voltage source, and U1 is a fast voltage comparator. With the inverting input of U1 (U1-) at zero volts, U1 OUT will go open-collecter when U1+ goes more positive than 0 volts, and to ground when U1+ goes more negative than zero volts. R2 pulls U1 OUT up to 5V, so as ACIN goes above and below 0 volts, ACLK will follow ACIN’s zero crossings and shuttle between 5V and 0V ijn step with ACIN.

S1 is a synchronous half-wave rectifier, and is gated ON and OFF through U2A by being turned ON when SWON and U3A-Q are both high, allowing ACIN’s positive half sinusoids to pass through S1 and into R1, where the voltage dropped across R1 is OUT, the circuits’s output.

However, when ACLK goes low and U3A-Q is high, SWON will go low, disconnecting OUT from ACIN, blocking the negative half cycles and referencing OUT to 0V through 10k ohms.

U2A ANDs ACLK with U3A-Q, the intent being that when U3A-Q is low, SWON and OUT will both be unconditionally low, regardless of the states of ACIN and ACLK. More on that later…

U6 is a 4 bit binary up/down counter used to control the number of OUT pulses per burst.

THE RESTING STATE:

Assume that the desired number of OUT pulses has occurred and that the counter’s output (Q3, Q2, Q1, Q0) has decremented to zero. In that case TC will be high, forcing CTEN high, which will freeze the counter at zero.

TC is inverted by U5C and is used to clear U3A, U3B, U4A, and to set U4B.

Clearing U3A forces U3A-Q low, forcing SWON and OUT low while ACIN and ACLK will remain active

THE ACTIVE STATE:

In order to start a new cycle, LOAD is momentarily pulled low

U3B, U4A, and U5A comprise a digital differentiator, which outputs a single single low-going pulse out of U5A, one ACLK period wide, when LOAD goes high after being momentarily pulled low by V3.

LOAD is also used to load the number-of-OUT-pulses data on the counter’s data inputs into the counter and, when that happens, TC will go low, enabling the counter, forcing STOP high.

Forcing STOP high releases the CLEAR on U2A, U2B, U3A, and the SET on U4B which will allow the pulse out of U5A to be syncghronized to ACLK and fed to U3A-SET.

U3A is being used as an R-S flip-flop, so the pulse on SET will force U3A-Q high, enabling ACLK to propagate through U2A and be used as SWON.

Notice that U6 has been enabled by LOAD and is just waiting for clocks to count its input data down to zero.

Notice also that CLK is SWON inverted, which means that for every positive half-sine pulse allowed through S1 while SWON is high, as soon as SWON goes low in order to block the negative half-sine, SWON will be inverted by U5B and will decrement the counter.

This process will continue until the count gets to zero, when the cycle will end until the next cycle is started anew by LOAD.

Just as an aside, I noticed that you said you don't use a simulator. Not trying to be a smartass or anything, but If you want to play this game and you learn how to use one you won't believe how much easier/funner it can make your life.

There's a learning curve involved, of course, but once you get past that it's "Hello world!"

LTspice is an excellent simulator, and it's freely downloadable at

http://www.linear.com/designtools/software/

Just for grins, I've attached all the files you need to simulate the half-sine burst generator, and all you'll have to do to get the sim to run, after you download and install LTspice, is to download them all into one folder and left-click on the .asc file.

Enjoy!
 

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