G Thread Starter gbox Joined Dec 29, 2015 42 May 23, 2016 #1 I have got the following circuit: I understood it is a OR gate, but in the case that V_1=V_2=contestant, V_out is equal to 2v_1=2v_2, unlike the situation when just D1 or D2 where open, is it still a "1" state or it is different because the V_out is bigger?
I have got the following circuit: I understood it is a OR gate, but in the case that V_1=V_2=contestant, V_out is equal to 2v_1=2v_2, unlike the situation when just D1 or D2 where open, is it still a "1" state or it is different because the V_out is bigger?
AlbertHall Joined Jun 4, 2014 11,960 May 23, 2016 #2 The output voltage cannot be more than the input voltages. If V1 = V2 then Vout = (V1 - Vdiode) * R/(R +r/2)
The output voltage cannot be more than the input voltages. If V1 = V2 then Vout = (V1 - Vdiode) * R/(R +r/2)
G Thread Starter gbox Joined Dec 29, 2015 42 May 23, 2016 #3 AlbertHall said: The output voltage cannot be more than the input voltages. If V1 = V2 then Vout = (V1 - Vdiode) * R/(R +r/2) Click to expand... Sorry forgot KVL law for a moment
AlbertHall said: The output voltage cannot be more than the input voltages. If V1 = V2 then Vout = (V1 - Vdiode) * R/(R +r/2) Click to expand... Sorry forgot KVL law for a moment