Hello, in a digital electronics exam, the following questions whas proposed:
Modify the following circuit to obtain a modulus 5 counter

The student answers like that:

But the teacher does not accept the answer arguing that the student has omitted the bubbles in the CLEAR input and the answer must be like the following

Is the teacher strict over the limit or no

 

hi a,
IMO the teacher is correct.
E

 

The teach is correct.
Read this:
https://forum.allaboutcircuits.com/threads/bubbled-inputs-and-ouputs.191699/#post-1796287

 

Is the teacher strict over the limit or no

The teacher is correct. The original solution decoded 5, but inverted the output, so the flip flops needed to have low active clear.

 

If you had omitted the bubble on the gate then it possibly would have been acceptable since the CLR logic was not specified.

 

First off, the "modification" involves changing the parts that are provided. The original circuit does not have clear or set inputs, so you are ostensibly swapping out the original parts with different parts. If you can do that, why can't you draw a completely different schematic using, say, D-type FF and call the result a "modified" circuit? In other words, what sets the limit on what is and is not a "modification"?

If you are able to assume that the original parts have accessible reset inputs, there's no reason why you can't assume that they are active HI or active LO. But for your solution to work, they have to be active-LO. Otherwise, the only time your circuit WON'T force a reset is when the two outside FFs are both outputting a HI.

 

First off, the "modification" involves changing the parts that are provided. The original circuit does not have clear or set inputs, so you are ostensibly swapping out the original parts with different parts. If you can do that, why can't you draw a completely different schematic using, say, D-type FF and call the result a "modified" circuit? In other words, what sets the limit on what is and is not a "modification"?

If you are able to assume that the original parts have accessible reset inputs, there's no reason why you can't assume that they are active HI or active LO. But for your solution to work, they have to be active-LO. Otherwise, the only time your circuit WON'T force a reset is when the two outside FFs are both outputting a HI.

By "modification", the teacher means that it is possible to "add" ASYNCHRONOUS INPUTS to the flip-flops circuit.

 

Is the teacher strict over the limit or no

No.
Your circuit will not work with the logic polarities shown.
Why do you think that's not important?

 

No.
Your circuit will not work with the logic polarities shown.
Why do you think that's not important?

No, I do not think that is not important. The parents of the student asked me if the teacher can "help" the student in the exam by giving him 1 point over the total 2 points of the question. Best regards

 

One obvious question that comes to mind having seen the student’s answer is “Why did the student show a NAND gate instead of an AND gate which would have received some credit?”

A problem with this asynchronous circuit is that you have to be careful with the meaning of “modulus 5 counter”. There is an output glitch when the counter reaches 5.

 

No, I do not think that is not important. The parents of the student asked me if the teacher can "help" the student in the exam by giving him 1 point over the total 2 points of the question. Best regards

That really depends on whether doing so represents equitable grading to the other students. The offered solution does show some degree of comprehension, but the solution still doesn't work. If other students that showed some level of comprehension, but not enough to get partial credit, did not receive partial credit, then neither should this student. Conversely, if they did, then this student likely should as well,

 

One obvious question that comes to mind having seen the student’s answer is “Why did the student show a NAND gate instead of an AND gate which would have received some credit?”

A problem with this asynchronous circuit is that you have to be careful with the meaning of “modulus 5 counter”. There is an output glitch when the counter reaches 5.

The student used a NAND gate because he probably remebered that in course the teacher used the same gate; but he probably forgot that the flip-flops have active low output CLR.

 

The student used a NAND gate because he probably remebered that in course the teacher used the same gate; but he probably forgot that the flip-flops have active low output CLR.

If this is the case, then the student deserves no credit in my opinion. Design by "remembering that someone somewhere used the same gate for something similar" doesn't cut it. They are just trying to regurgitate answers with no real comprehension.

 

They are just trying to regurgitate answers with no real comprehension.

Yes.
Rote learning without understanding is basically useless.

 

One obvious question that comes to mind having seen the student’s answer is “Why did the student show a NAND gate instead of an AND gate which would have received some credit?”

A problem with this asynchronous circuit is that you have to be careful with the meaning of “modulus 5 counter”. There is an output glitch when the counter reaches 5.

True on the glitch. I thought it might be useful to the TS to point out that in a synchronous circuit this glitch may not matter as on the rising edge of the 5th clock the output is still 100b and that gets latched into the next register and the next rising edge the output is 000b thus in a synchronous system it should not matter.
Also, the way this counter is wired makes each transition a possible 'glitch' as it takes the output of one gate to 'clock' another one. There is technically glitches during the entire counting process.

 

In a synchronous design the output goes from 100 to 000. There is no 101 state.

In the asynchronous design there is a short glitch when the output reaches 101.

 

In a synchronous design the output goes from 100 to 000. There is no 101 state.

In the asynchronous design there is a short glitch when the output reaches 101.

What I meant by a synchronous design: the output of the counter is registered via a 3 bit register on the next clock edge, thus no issues. You are correct in the glitch in fact there is a glitch going from 001b to 010b as there is a glitch of 000b between them and many others along the way from 000b to 100b

 

Bad teacher.

It is incorrect to async reset a synchronous counter. There are 6 states in the solution, not five. One is unstable.

I would teach this as an example of what not to do.

 

In general, whenever asynchronous inputs are used, the glitch behavior must be considered very carefully. In a ripple counter, the order in which the outputs change is pretty deterministic, but in a synchronous counter the possibility that the set of outputs that change can change in any order must be allowed for. In either case, if the outputs are decoded to produce an input to an asynchronous input (such as a set/reset or a clock input) then ALL of the possibilities must be considered.

This is why I hate the common practice of teaching students to design ad hoc asynchronous logic. That should only be done far enough to make the point that it should never be done without a damn good reason and that it is an advanced topic, then turn the focus to properly designing fully-synchronous solutions. A discussion of the pros and cons of asynchronous versus fully-synchronous logic is completely appropriate, since there ARE significant advantages to asynchronous logic, and hence damn good reasons do exist for using it. This is another example of teachers and (textbook authors) having little to no real-world experience and living in an ivory tower where they can blindly assuming that things will work they way they would like them to on paper. The result is that students graduate with the engrained impression that it is fine and proper to use asynchronous inputs and gated clocks without any consideration whatsoever for glitch behavior. Worse, this is almost inevitably coupled with scant coverage of glitches at all, usually relegating static and dynamic timing hazards to a portion of one lecture and the considering that box checked because the instructor sees it as an esoteric topic in the same vein as things like existence and convergence proofs in a math class.

 

In a synchronous design the output goes from 100 to 000. There is no 101 state.

In the asynchronous design there is a short glitch when the output reaches 101.

True the counter itself is asynchronous, but if you only look at the counter output on the rising edge of the clock it does not matter. As shown in the following with the output taken from A,B and C.