Odd Biasing on a Digital Circuit

Thread Starter

SamR

Joined Mar 19, 2019
2,126
Playing with some circuits and was laying out an S-R Flip-Flop and noticed that the Voltage flow was backwards? The inputs grounded and the outputs have +5V on them. Is this typical or even normal usage? My head is telling me it is backwards! I also had to add pullup resistors on the inputs to make it work.

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AnalogKid

Joined Aug 1, 2013
8,464
the Voltage flow was backwards?
Not sure what you mean by that. Functionally, a 7400 NAND gate is an AND gate followed by an inverter. When either (or both) of its inputs are low, the output will go high. Or try to, depending on the load it is driving. Note that 7400 series TTL has very asymmetrical input and output conditions. an output can sink 16 mA, but is required to be able to source only 1-2 mA (working from memory).

Another note - With a Set-Reset NAND flipflop, it is possible and valid for both outputs to be high at the same time. If you hold both inputs low, both outputs will go high. There is no valid condition for both outputs to be low at the same time.

Snotty pedantic note: It isn't voltage flow, and it isn't current flow; it is electron flow. By difinition, a current is a flow, so the common term "current flow" is redundant. Like "PIN number" is redundant because the N in PIN already stands for Number.

ak
 

Thread Starter

SamR

Joined Mar 19, 2019
2,126
I thought about saying biasing but... Bottom line is I expected the outputs to go to ground and not the +5.
 

crutschow

Joined Mar 14, 2008
24,968
OK that I can take as reasonable. Just never thought of them as a sink device in that manner.
It's because, to generate a logic low at a TTL input you need to sink current to ground, but it takes little or no current to generate a logic high.
 

AnalogKid

Joined Aug 1, 2013
8,464
Old TTL derived from older DTL (diode-transistor logic), which derived from even older RTL (resistor-transistor logic). Without any historical context, a standard TTL input stage is ... non-intuitive. You sink current out of it to turn on a common-base amplifier. How analog is that!

A consequence of this is that there is a minimum amount of current that must be sucked out of a TTL input for the input to be recognized as being in a logic-low state. That current is 1.6 mA, which is why a standard TTL output can sink 16 mA (Ten-stage drive capability was already establised as an industry standard.). If you want to tie an unused input to GND, the resistor must be under 500 ohms. 220 ohms provided a nice, firm low, but increased input stage power dissipation. 470 ohms was barely enough, and increased noise sensitivity. 330 ohms was a common compromise value.

ak
 

Thread Starter

SamR

Joined Mar 19, 2019
2,126
Hmmm... And if I remove the pullups and take S1 to +5 through a pullup resistor I can reverse the action. Interesting...
 

Thread Starter

SamR

Joined Mar 19, 2019
2,126
I have digital on the to-do list but still a few more things get done first. Thanks guys.
 

MrChips

Joined Oct 2, 2009
21,126
You must pay attention to the xxx letters as in 74xxx00 series as they make a huge difference in supply current, voltage, input/output currents and max operating frequencies. Also many series are not compatible with other series.

As AK says, input currents are much higher for 7400 series chips.

For plain garden variety 7400, pull down resistors should be about 220Ω.
Pull up resistors are about 2k to 5kΩ, not 500kΩ.
 

MrChips

Joined Oct 2, 2009
21,126
Hmmm... And if I remove the pullups and take S1 to +5 through a pullup resistor I can reverse the action. Interesting...
Actually, no.

It would not work with pullups on a switch connected to +5V unless the pullup is much lower in value than the 220Ω pulldown which is still required.

If you want to reverse the action, swap the two LEDs.
 

WBahn

Joined Mar 31, 2012
25,760
I thought about saying biasing but... Bottom line is I expected the outputs to go to ground and not the +5.
The outputs try to be at either 5 V relative to the "ground" pin of the chip, or at 0 V relative to that same pin. In practice, TTL can't make it all the way to 5 V, even with no load, because of the design of the output stage. Somewhere around 3.5 V is more typical. As already noted, it can't source much current when it's HI, but it can sink a fair amount when it is LO. So you want the load to be active when the output is LO, which is why the LED is oriented the way that it is.

In theory, the inputs to TTL gates are intrinsically pulled high by the nature of the circuitry. In practice, this even works from time to time. It is always best to NEVER leave a logic input floating unless it is specifically designed to be used that way (and there are many instances where that's the case).

While it won't affect this circuit, you also want to make sure that your switch is break-before-make (which most SPDT switches are, but there are exceptions), otherwise you will take your logic into the "disallowed" state with both set and reset asserted.
 

Thread Starter

SamR

Joined Mar 19, 2019
2,126
Yes, I was actually using an old SN74HC00. I usually work with the CD series. Looks from the PDF it can only sink 20mA and source 25mA.
It would not work with pullups on a switch connected to +5V unless the pullup is much lower in value than the 220Ω pulldown which is still required.
It does work by removing the 2 pullups and placing one of them from S1 common to +5v which reverses the action. I did change to 2K on the pullup.

He did not mention anything about floating pins so I initially did not do anything with them. I later added pulldowns to the floating inputs as specified by the PDF as on the breadboard it does seem to be a bit flaky or more so than the typical quasi-loose plugin connections.

Lost my house internet so having to use the cell as a hotspot for now...
 

MrChips

Joined Oct 2, 2009
21,126
Yes, I was actually using an old SN74HC00. I usually work with the CD series. Looks from the PDF it can only sink 20mA and source 25mA.

It does work by removing the 2 pullups and placing one of them from S1 common to +5v which reverses the action. I did change to 2K on the pullup.

He did not mention anything about floating pins so I initially did not do anything with them. I later added pulldowns to the floating inputs as specified by the PDF as on the breadboard it does seem to be a bit flaky or more so than the typical quasi-loose plugin connections.

Lost my house internet so having to use the cell as a hotspot for now...
Hmmm... And if I remove the pullups and take S1 to +5 through a pullup resistor I can reverse the action. Interesting...
Above is YOUR statement. Emphasis in RED added.

Of course, if you remove through a pullup resistor it will work. Because now your through a pullup resistor is 0-ohms which is lower than the pulldown resistor of whatever value >0.
 

AnalogKid

Joined Aug 1, 2013
8,464
Yes, I was actually using an old SN74HC00.
HC stands for High-speed CMOS. While it does function as a NAND gate, internally it is *completely* different from the 7400 device on your schematic. Zero percent of the above internal circuit descriptions apply to that part.

HC series logic gates are completely CMOS inside, with old TTL pin assignments. If you check both datasheets, you will see that the 7400 and 74HC00 pinouts are the same, but the input and output characteristics are different. If you compare the CD4011 and the 74HC00 pinouts, you will see that they are different.

ak
 

MrChips

Joined Oct 2, 2009
21,126
No, No, No!

220Ω is used to PULL-DOWN a 7400 input.

If you are using 74HC00 you can use just about any PULL-UP value.
Your original 500kΩ in post #1 will work.
10k - 22k - 100kΩ will all be fine in post #1 circuit. Do not use circuit 1 or 3 in post #17.

You need to explicitly state in your drawing that you are using 74HC00 and not 7400.
 

WBahn

Joined Mar 31, 2012
25,760
Never, ever, EVER leave "normal" CMOS inputs floating. It is asking for all kinds of problems -- problems that can destroy the chip. You can only leave them floating if the data sheet explicitly states that it is okay to do so.

This also includes the unused inputs on unused gates in the same package, such as the other two NAND gates in your 74HC00 part. If a CMOS chip is powered, then ALL of it's inputs should be at defined logic levels.
 
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