Hi

Please have a look on the attachments. You can find my two questions there. Please help me with them. Thanks a lot.

Regards
PG

 

This is an example of DeMorgan's Theorems.
There are two ways to look at digital signals and logic: positive logic and negative logic. Also signals can be ACTIVE-HI or ACTIVE-LO.

Here is an example of positive logic: If it is sunny AND my bike is working I will go for a bike ride.

Here is the same logic using negative logic: If it is not sunny OR my bike is not working I will not go for a bike ride.

Sometimes it is easier for humans to think in terms of positive logic. So the left hand symbol is an AND gate with an ACTIVE-LO output.

The right-hand symbol is an OR gate with ACTIVE-LO inputs.

When a signal is ACTIVE-HI it requires a high voltage to perform the function.
When a signal is ACTIVE-LO it requires a low voltage to perform the function.

Suppose we want to RESET a circuit using either a RESET push-button that shorts to ground or a reset from a POWER-ON-RESET circuit. Suppose these are all ACTIVE-LO signals. Then the proper gate is an OR gate with ACTIVE-LO inputs and an ACTIVE-LO output. (It is not to be regarded as an AND gate).

Note that both the bar over the signal name and the bubble indicate that the signal is ACTIVE-LO. The bar is considered part of the name, just as RESET'. It is not to be considered as NOT RESET.

 

Thank you, MrChips. I appreciate your help.

I request you to correct me if I'm wrong.

Okay. Simply put, the bubbles on the inputs or outputs are there only to inform us how proper connections are to be made, how the circuit works or how certain function is to be perfomed such as a reset. When there is a bubble it tells logic is ACTIVE LOW and when there is no bubble it informs it's ACTIVE HIGH logic.

But have a look on this 2-input OR gate below. As there are no bubbles on inputs or output, it means when both inputs are at ACTIVE HIGH state, output is also at ACTIVE HIGH state. This is how 'normal' OR is represented.

But the negative-OR which is nothing more than a NAND gate, we have a special case. When both inputs are LOW we get HIGH output, and when both inputs are HIGH we get LOW output. This is what differentiates a normal OR gate from a negative-OR gate. So, using your example, "Even if it's raining OR there is a cyclone, I would still go to see Sally at the airport".

Thanks a lot for the help.

Best regards
PG

 

But the negative-OR which is nothing more than a NAND gate, we have a special case. When both inputs are LOW we get HIGH output, and when both inputs are HIGH we get LOW output. This is what differentiates a normal OR gate from a negative-OR gate.

Not quite right.

A negative-OR as shown in post #2 must not be considered as a NAND gate (even though it may be implemented with a 7400 NAND gate).
A negative-OR as shown in post #2 is an OR gate with ACTIVE-LOW inputs
The output is TRUE (HIGH) if either input is ACTIVE-LOW.

So your statement should read:
"When EITHER input is LOW we get HIGH output"

The equivalent statement for a positive logic OR gate would be:
"When EITHER input is HIGH we get HIGH output"

 

"Even if it's raining OR there is a cyclone, I would still go to see Sally at the airport".

This makes no sense to me.
What your logic tells me is if it is not raining and there is no cyclone, Sally is stuck at the airport without you.
What you have to determine firstly is, is it an AND condition or an OR condition you want to convey?

 

Once again, my thanks, MrChips, for the help and kindness.

Not quite right.

A negative-OR as shown in post #2 must not be considered as a NAND gate (even though it may be implemented with a 7400 NAND gate).
A negative-OR as shown in post #2 is an OR gate with ACTIVE-LOW inputs
The output is TRUE (HIGH) if either input is ACTIVE-LOW.

So your statement should read:
"When EITHER input is LOW we get HIGH output"

The equivalent statement for a positive logic OR gate would be:
"When EITHER input is HIGH we get HIGH output"

I don't really get it. Negative OR logic cannot be implemented using normal OR gate which is used for implementation positive OR logic. When a NAND gate is used to implement negative OR logic, it is given a special symbol. But it's still very much a NAND gate. I think it's only a matter of interpretation. Isn't it?

So, as you say, there exists two types of logic: positive logic, negative logic. So far I have only read about positive logic, at least it seems so! How would differentiate between the two and under what conditions which one of the two would be preferable over the other? Could you please help me with it?

This makes no sense to me.
What your logic tells me is if it is not raining and there is no cyclone, Sally is stuck at the airport without you.
What you have to determine firstly is, is it an AND condition or an OR condition you want to convey?

I was trying to use negative OR logic.

Sally is not stuck at the airport. She is coming back from some place. Paradoxically, when there is no rain or there is no cyclone, let's say, John wouldn't be there to receive Sally; although otherwise John would go to the airport even if both hell and earth unleash themselves!

Best wishes
PG

 

Here is another example. Imagine you have two push-buttons that operate a door bell. The bell rings when EITHER the front door OR the back door button is pressed. The signals from both push-buttons are ACTIVE-LOW, that is, a LOW voltage indicates that the button is pressed.

The proper logic function is an OR gate with ACTIVE-LOW inputs as shown. The gate is implemented with a 74LS00 NAND gate. It is easier to understand the logical operation of the circuit when the proper DeMorgan equivalent gate is drawn.

 

 

A technique that is commonly used when trying to simplify or analize logic circuits by "eye-balling" is to think of bubbles as beads on a wire.

1. You can slide a bead forwards or backwards along the wire.
2. When one bead encounters another they cancel.
3. You can insert a pair or beads on the same wire without changing the logic function.