Came across this component. Never heard of a D-MOS transistor

Here's a data sheet:
https://assets.nexperia.com/documents/data-sheet/BSP250.pdf
It comes out of an old smoke detector (Ionization detector type)
Reading the DS I can see it's for switching power. Aside from what the DS tells me I know nothing about it. OK, it's a P-MOS enhancement mode FET. What I don't understand is the "D" in D-MOS. P-MOS, N-MOS, those I know. Just not the D-MOS.

And what's the "Vertical"?

 

Hello,

Does this help?
https://techweb.rohm.com/trend/glossary/16540/

Bertus

 

Yes. Somewhat. It also helps with the confusion. Can a DMOS be PMOS or NMOS? What is double diffused? I've seen illustrations of a common MOSFET and understand how they work. But vertical? Horizontal? I need a picture for clarity. I'm imagining in "horizontal" P & N dopes are one on top of the other (in parallel sort of - maybe) where vertical is side by side with the gate along side?

This isn't anything critical, just discovered this thing and I don't know what it is. Truth be told, there are a lot of things I don't know. Things I don't even know I don't know. But since some knowledge of N & P MOS's exists between my ears, I have to ask about D MOS. Double diffused? Vertical? Horizontal? It's entirely new to me.

 

They are extraneous, like the j, m, and i in your spelling of education.

 

Hello,

Here is a page with some pictures:
https://www.rfwireless-world.com/terminology/rf-components/dmos-vs-vmos-vs-ldmos

Bertus

 

Yes. Somewhat. It also helps with the confusion. Can a DMOS be PMOS or NMOS? What is double diffused? I've seen illustrations of a common MOSFET and understand how they work. But vertical? Horizontal? I need a picture for clarity. I'm imagining in "horizontal" P & N dopes are one on top of the other (in parallel sort of - maybe) where vertical is side by side with the gate along side?

This isn't anything critical, just discovered this thing and I don't know what it is. Truth be told, there are a lot of things I don't know. Things I don't even know I don't know. But since some knowledge of N & P MOS's exists between my ears, I have to ask about D MOS. Double diffused? Vertical? Horizontal? It's entirely new to me.

https://patents.google.com/patent/US3346428A/en
Method of making semiconductor devices by double diffusion

Simply put, when you dope transistors it can be a 3D defined structure instead of a single plane of PN junction. In the old days of semi process technology, most junctions were create using a dopant gas or liquid that mainly affected the surface and slowly diffused into the substrate. to push it deeper you needed a very long 'drive' process anneal (heating the silicon until the locked lattice becomes malleable) in addition with created shields to shunt the materials to the correct places.

It's still used today on specialty devices but the epi process is nasty and potentially dangerous when things go wrong, and they do.
https://www.appliedmaterials.com/eu/en/semiconductor/semiconductor-technologies/epitaxy.html

Today we still do much the same but we can have a single quick process step that eliminates most of the structure building diffusion processes and gives exact control for 3D structure building with dopants. It's called Ion Implantation. We can also use this process for precision 'drives' to push ion into place, move them around of make them diffuse deep in the device structure with high energy ions in the MeV range. Ion Implantation makes building modern devices possible, once the stepper makes the build patterns.

https://semiengineering.com/knowledge_centers/manufacturing/process/ion-implants/

There are three main segments in the overall implanter market: high-current; medium-current; and high-energy. High-current implanters are used for source/drain development. Medium-current tools are used for well implants. High-energy implanters are used for deep well implants.

 

WOW! Where have I been technology wise. Lots of great information. Thanks so much for all the responses. MUCH appreciated.

 

In transistor structure and process the word diffusion should be discussed some
the added impurities are made to spread to just the right spots.
Generally, spreading dopants the wafer is heated, causing the dopants from ion implantation to move
and settle into their final positions within the silicon structure and a half plane is mirror image or Double.

The less than production appropriate DMOS transistor was released in 1955.
Modifications to that technology way back in 2024 were referred to as
teaching an old dog new tricks. The right to repair, how old is that in R&D?
I am not sure where you have been. I mostly remember those having to go silent.

 

In transistor structure and process the word diffusion should be discussed some
the added impurities are made to spread to just the right spots.
Generally, spreading dopants the wafer is heated, causing the dopants from ion implantation to move
and settle into their final positions within the silicon structure.

The DMOS released in 55, the latest modifications 2024 were referred to as
teaching an old dog new tricks. The right to repair, how old is that in R&D? What are the stakes?

That's old school. Today we can channel the dopants exactly where we want them and then do the RTP (using high power lamps that work in seconds per wafer instead of hours with a traditional furnace) to repair the lattice damage from the implant process or to build layers.


https://en.wikipedia.org/wiki/Rapid_thermal_processing

It's pretty cool to watch the wafers jump during the processing. I've made upgrades for the old RTP machines with X/Y lamps to improve uniformity but they can't come close to what's possible with newer equipment.
Old with DTC wafer temp control. Oldest machines still running in a typical lagging technology fab, I worked on them back in the 5" wafer era, back when the OEM was still alive.


New

 

Oh no, Thanks NSA you got me. I am also behind ,Wow, where have I been?
after viewing the video on the nice Applied Materials Centura reactor. Reviewing the significant variety in the DMOS family,
I concede that I cannot find a problem in future growth in DMOS. I thought there was a problem in multi-layer masking but they successfully used lateral and vertical,
That is LDMOS and VTMOS resolving HV issues for electric vehicles, power electronics, and even reaching 10GHz.

I really need to re-adjust my thinking to the process side especially on what the later generation could resolve.
Building external discrete is as close as I can get to this.
Attachment

 

Somewhere, aside from all of the wonderful manufacturing processes, are also modes of operation, which include the "enhancement mode" and the "depletion mode", which relates to the input (gate) voltage changing the availability of charge carriers. And while my involvement with the manufacturing process is less than yours, involvement with circuits that affect changes in the current is closer . That involves convincing the gate to vary the amount of charge carriers.

 

Oh no, Thanks NSA you got me. I am also behind ,Wow, where have I been?
after viewing the video on the nice Applied Materials Centura reactor. Reviewing the significant variety in the DMOS family,
I concede that I cannot find a problem in future growth in DMOS. I thought there was a problem in multi-layer masking but they successfully used lateral and vertical,
That is LDMOS and VTMOS resolving HV issues for electric vehicles, power electronics, and even reaching 10GHz.

I really need to re-adjust my thinking to the process side especially on what the later generation could resolve.
Building external discrete is as close as I can get to this.
Attachment

A few years from now it will be old school too. Technology marches on and prices for new tools goes up.