Hello:

The datasheet link for HCT573 is as follows:
SNx4HCT573 Octal Transparent D-Type Latches With 3-State Outputs datasheet (Rev. G) (ti.com)
I'm currently working on a digital circuit design and have encountered a challenge. There seems to be a discrepancy between the behavior of a D flip-flop and a D latch; specifically, one operates on edge triggers, whereas the other is level-triggered. Unfortunately, when browsing through the Digital component library in LTspice, I've only been able to locate a D flip-flop component. This has left me at a standstill, as I'm unsure how to proceed without access to a D latch. Any insights or suggestions would be greatly appreciated!

Thanks!

 

Any insights or suggestions would be greatly appreciated!

What is there to simulate?

When LE is HIGH, the latch is transparent, when LOW, it latches:


If you feel so uncertain of your skills that you need a simulation to do the thinking for you, you can make a latch with gates.

 

What is there to simulate?

When LE is HIGH, the latch is transparent, when LOW, it latches:
View attachment 312171

If you feel so uncertain of your skills that you need a simulation to do the thinking for you, you can make a latch with gates.

Thank you for your reply and suggestions, I will try it as soon as possible.

 

The output waveform looks a bit strange, why isn't it regular? What did I do wrong? See the model file at try_HCT573.asc.

 

Hi @zeros
You need to add the VHigh and Vlow to the digital devices.
Also the 74VLC1G126 device does not work as expected, requires a PU resistor?

Clip:
Description
The 74LVC1G126 is a single, non-inverting buffer/bus driver with a
3-state output. The output enters a high-impedance state when a
LOW level is applied to the output enable (OE) pin. The device is
designed for operation with a power supply range of 1.65V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed-voltage environment. The device is fully specified for partial
power down applications using IOFF . The I OFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.

 

Hi @xeros.
This sim is for the 74LVCG126.
Try setting V3 at 0V and 5V, see the effect on the op1 output, it appears to be a model problem??
Also try removing the 5k resistor.
E

 

Hi @zeros
You need to add the VHigh and Vlow to the digital devices.
Also the 74VLC1G126 device does not work as expected, requires a PU resistor?

Clip:
Description
The 74LVC1G126 is a single, non-inverting buffer/bus driver with a
3-state output. The output enters a high-impedance state when a
LOW level is applied to the output enable (OE) pin. The device is
designed for operation with a power supply range of 1.65V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed-voltage environment. The device is fully specified for partial
power down applications using IOFF . The I OFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
View attachment 312198

After running the file you modified, I noticed that the output voltage waveform of Q differs from what you expected. A peculiar bug has emerged, as evidenced by the output waveform image.

 

I'm stunned!

 

Hi zeros,
The oe glitch is due to the slow response times of the digital models in LTSpice.

The final output signal looks correct, so the glitch should not present a problem in simulation.

Which part is making you 'stunned' ?
E

 

@ericgibbs What shocked me was not the oe, but the waveform of the Q signal.

 

@ericgibbs

 

Hi zeros,
I am sorry, I do not know what you mean, what is the problem you see for the Q signal.

Note: for setting the parameters of the Digital logic, use the Help Option.

E


@zeros.
OK, I see your last post, I will see what I can do.

 

Hi @zeros
You need to add the VHigh and Vlow to the digital devices.
Also the 74VLC1G126 device does not work as expected, requires a PU resistor?

Clip:
Description
The 74LVC1G126 is a single, non-inverting buffer/bus driver with a
3-state output. The output enters a high-impedance state when a
LOW level is applied to the output enable (OE) pin. The device is
designed for operation with a power supply range of 1.65V to 5.5V.
The inputs are tolerant to 5.5V allowing this device to be used in a
mixed-voltage environment. The device is fully specified for partial
power down applications using IOFF . The I OFF circuitry disables the
output preventing damaging current backflow when the device is
powered down.
View attachment 312198

@ericgibbs

In the waveform results you provided, Q is 5V in the time period of 4-10ms. However, in my output waveform, it is 0V in the time period of 4-7ms and 5V in the time period of 7-10ms. I'm not sure if you have noticed this difference, please forgive me for not clarifying this earlier.

 

Hi zeros.
I have rerun my asc sim and I see this waveform result.
Please post copy of your asc file .
E

 

This is the file I am using.@ericgibbs

 

Hi z,
To check the logic, I have converted the circuit to 74HCT logic and added a plot of the input inp to the 74VLC.
This shows my version of the original circuit is giving the same correct result.

Do you have the 74HCT library in your LTSpice?

I will try your latest asc file, let you know the result.

E

 

Hi z,
This is your asc file simulation in my PC, it looks OK.

There is a problem in your LTSpice installation or your PC.
E

 

Tip: If you do experience timing glitches/hangups with the Digital devices (but I don't think that's the issue here), giving the Tau parameter a small value can often be a solution.

 

@ericgibbs First of all, thank you very much for helping me solve this problem. I ran it on another computer, and the output waveform didn't change at all. I suspect there might be an issue with the associated model file 74LVC1G.lib. Could you try the entire project file that I uploaded? I don't think there's a problem with the usage of logic gates because the inverted Q signal is correct.

 

hi zeros.
Using only the files in your zip file of post #19, this is what I see, it looks OK.
E