- Joined Oct 2, 2021
IanO, aside from my desires to achieve linear amp. using a FET transistor, I'd like to ask you: is the accepted method of amp. with a JFET to bias the gate along the transconductance curve somewhere between pinch off and zero volts Vgs. And voltage divider biasing of the gate should never be close to the pinch off voltage of the FET channel. Just enough to keep the signal from forward biasing the FET gate? If you'd like to share the equation for calculating the Siemens from data sheet zero gate volts, rated Vsd, and rated mAdc drain current, it would be much appreciated. My legal name is David E. Furlong, you might have heard the name Kevin Furlong; he's a brother who gave me this sites name.