making an SPDT switch using mosfets

Thread Starter

robintes

Joined Feb 20, 2023
13
I see this has been asked a few times but answers have been only bits and pieces of the puzzle. Clearly I want to replace a mechanical toggle switch or relay with a solid state equivalent - In all respects of functionality, ie the control sig (your finger or energise solendoid) is isolated, the output is two independant isolated conductive channels that hold their state. There must be no s/c overlap during transition - no momentary short at all across channels - entirely break before make under all cases. On de-energising (power off) the mosfet cct should reset to a known condition.
Hope that covers it - but I have a suspicion - not everything.
:-//


The ccts I have seen tend to trivialise the changeover state and its possible failure (s/c even for usecs). There is the impact of noise and spikes to consider that could trip the state for example.
My concern is with switching Lipo cells so for basic SOR use 5Vdc source and 5A switch current with 10A load. Assume that a separate fault interrupt cct exists. Switching frequency <20kHz maybe 5kHz square wave 50% duty.

I dont want to resort to a Micro with s/w control the cct. A 555 clock should be fine.

I was thinking that an A or B state becoming ON should be enabled first by the other channel being confirmed as OFF with a suitable delay time between.

Sorry if this is a bit scrambled, I dont want to over shadow creative thought by fresh minds

You would think somehow this would obviously be available
:-//


Robin
 

eetech00

Joined Jun 8, 2013
3,955
Are you asking for a solid state switch with independent NO and NC contacts?

use an optocoupler to drive a mosfet of your choice.
However, unless precisely matched components are used, there will be some overlap between one contact opening and the other closing.
A SSR would be a better choice.
 
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crutschow

Joined Mar 14, 2008
34,457
Below is the LTspice sim of a circuit using a high-speed opto isolator input, and a non-overlap circuit driving two high-side P-MOSFETs:
The values of R3*C1 and R1*C2 determine the non-overlap time (here about 2.5µs).
The P-MOSFETs can be any logic-level type that meet your voltage and on-resistance requirements.

Will that work for you?

1703399498205.png
 
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LowQCab

Joined Nov 6, 2012
4,075
This type of Switching is literally everywhere.
If You would state the purpose of your project
You would very likely get more useful answers.
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LowQCab

Joined Nov 6, 2012
4,075
No, no one knows what you're talking about, because You haven't told us yet.

What is your project supposed to do ?
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crutschow

Joined Mar 14, 2008
34,457
Won't that solution require the two MOSFET sources to connect to respective power supplies?
Of course, as long as they both have a ground common to the circuit.
I showed one source just for the sim.

Below is the sim with two slightly different source voltages so you can see from the load current which one is energized:

Which brings up the note that if there is more than about 0.5V difference between the two voltage sources, then two back-to-back MOSFETs must be used for each switch to prevent one source from driving the other through their substrate diodes.

1703452367582.png
 
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Thread Starter

robintes

Joined Feb 20, 2023
13
Hi LQC
I purposely stayed away from discussing my usage of a SS relay cos I didnt wan this OP to get side tracked into discussing my particular interests. IMHO its important to focus on the fundamentals of the OP namely to get an SS emulation of a std em relay spdt with particular attention to preventing overlap and shorting of output contacts. It must be "break before make" under all cases. eg what happens with power off. Examine the difference between momentary (push button) and latching (sr relay)
 

Thread Starter

robintes

Joined Feb 20, 2023
13
Hi @crutschow thnx for your input. Schmitt triggers have useful properties. The feedback NOR cct needs careful analysis. The TI data book https://www.ti.com/lit/an/scha004/scha004.pdf?ts=1703407340153&ref_url=https%3A%2F%2Fwww.google.com%2F shows that noise is a concern for this type of solution. How sure are you that this will work at mission critical level? Will a glitch result in a catastrophic s/c between output contacts - even for a usec.?

You see an E/M relay is quite robust in that respect (saving a contact weld).

For the purpose of the OP consider the output chA chB to be separate lamps not a single load - your cct is for a repeating control sw input. Remove the opto/isol coupler - not needed just now - get back to the simplest implementation KISS. We need the cake right well before any icing.

1703462683470.png

I hope this shows the essence of the OP - now convert this into a SS relay. A robust utterly reliable cct
 

crutschow

Joined Mar 14, 2008
34,457
Where exactly does it say that for this type of solution?
CMOS gates are quite noise resistant, usually near 1/2 the supply voltage.
How sure are you that this will work at mission critical level?
So how critical is the mission?
Will a glitch result in a catastrophic s/c between output contacts - even for a usec.?
It would have to be a glitch picked up at the input to one of the gates equal to 1/2 the supply voltage.
Since the gate inputs are being driven by a low-impedance gate output, you would need to be in a extremely high-power, noisy EMI environment to get that level of glitch.
Are you designing for it to tolerate the EMP from a nearby nuclear explosion? :eek:
Your concern about noise, and your mention of "mission critical level" would seem to indicate you are. :rolleyes:
 
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Thread Starter

robintes

Joined Feb 20, 2023
13
You seem to take the opposite view point to me, whereby you assume that your design is perfect for the requirements - so how do you prove it? The more complex you make your ccts, the more potential points in the fault tree you create and so it rises exponentially. Imagine the case where your cct is controlling a bomb, so if it fail, a loss of life/property occurs - then re-think your cct. This is where your bench sim goes into real life and your hapless User becomes the Proof Tester. Bench Sims are only the first line in validation and are well known for being only an approx case study tool.

Now wrt your fli flop cct, it doesnt contain a master clock and so may not provide reliable operation under continuous state
Have you considered the case where S=R=1 during xover of U1 and U2

For logic ics to work reliably they must be checked for state when a change impulse has settled down electrically (conventionally using a master clock at the steady state period)

I have shown my basic requirements, now start from a blank sheet of paper and create a SS relay
 

LowQCab

Joined Nov 6, 2012
4,075
All Circuits, and the Specific-Components used to create them,
must be "tailored" to the specific requirements of the "problem" to be solved.

If You don't care to divulge the "problem" that You are trying to solve,
you're on your own,
and You are wasting everyone else's time and efforts.

You might be excused if you're new to Electronics,
and that seems to be the case, based on your approach so far.
In that case, You could take away something useful and valuable from all of these interactions.
But as to whether or not You will actually learn something remains to be seen.
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Ya’akov

Joined Jan 27, 2019
9,170
You seem to take the opposite view point to me, whereby you assume that your design is perfect for the requirements - so how do you prove it? The more complex you make your ccts, the more potential points in the fault tree you create and so it rises exponentially. Imagine the case where your cct is controlling a bomb, so if it fail, a loss of life/property occurs - then re-think your cct. This is where your bench sim goes into real life and your hapless User becomes the Proof Tester. Bench Sims are only the first line in validation and are well known for being only an approx case study tool.

Now wrt your fli flop cct, it doesnt contain a master clock and so may not provide reliable operation under continuous state
Have you considered the case where S=R=1 during xover of U1 and U2

For logic ics to work reliably they must be checked for state when a change impulse has settled down electrically (conventionally using a master clock at the steady state period)

I have shown my basic requirements, now start from a blank sheet of paper and create a SS relay
You have decided that one of the most important and most often repeated (on AAC) ideas concerning design questions, learned from many years of experience, is simply unimportant.

When starting out to design anything to solve a problem, the problem must be clearly stated. You have turned your solution into the problem—a common error. Your problem is not trying to designa break-before-make, completely reliable, MOSFET switch it’s something else, barely revealed by mentioning LiPo batteries.

You are asking for help, people are asking for more information which is really only going to be properly revealed by a description of the problem this is expected to solve. (Not the specs you‘ve decided on, the application of it.) If you could do this yourself you wouldn’t need to ask. Since you can’t do it yourself it is hard to understand why you think you are qualified to determine what information is needed to design a solution.

From the perspective of a potential helper your approach is arrogant and entitled. You might benefit from some introspection. It would be very helpful to those who are trying to help you if you would describe the problem you expect this to solve. Many times, thanks to the surprisingly vast store of experience AAC provides, an unexpected solution arises thanks to the many different points of view the members here enjoy.

One more thing, not important in the grand scheme, but it compounds the already rankling nature of your posts: please avoid non-standard abbreviations, and abbreviations that might be standard in some contexts but are out of place in a forum post where written out text is expected. It makes your posts hard to parse.
 
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