Hello
I am trying to show how I can pull a the EN/UVLO pin low using an NMOS. I did the voltage divider equation to find that Vgate will be about 12V when Vbattery is 13.5V. However as shown in the simulation that is not the case when I include the zener diode, I didnt think it would have much effect since the listed Rs of the diode is 0.5ohms. Why is my gate not reaching the desired gate votlage to turn this NMOS on?
Also, I would like to show that the EN/UVLO pin listed in the diagram can start at a higher voltage, and then be pulled low when the NMOS is turned on. However, using a voltage source just keeps it a constant 10V. Is there a better way to show how a pin can be pulled low to ground once the short is established by the NMOS turning on?
View attachment 282145
With zener diode in simulation:
View attachment 282146
Without zener diode in simulation:
View attachment 282147
I am trying to show how I can pull a the EN/UVLO pin low using an NMOS. I did the voltage divider equation to find that Vgate will be about 12V when Vbattery is 13.5V. However as shown in the simulation that is not the case when I include the zener diode, I didnt think it would have much effect since the listed Rs of the diode is 0.5ohms. Why is my gate not reaching the desired gate votlage to turn this NMOS on?
Also, I would like to show that the EN/UVLO pin listed in the diagram can start at a higher voltage, and then be pulled low when the NMOS is turned on. However, using a voltage source just keeps it a constant 10V. Is there a better way to show how a pin can be pulled low to ground once the short is established by the NMOS turning on?
View attachment 282145
With zener diode in simulation:
View attachment 282146
Without zener diode in simulation:
View attachment 282147
Last edited: