Hi,

As the title states, I'm trying to built a solar powered USB charger and so far it works quite OK. I also tried my best to include a "Voltmeter" to monitor the amount of Volts the solar panel supplies. The current state of the project looks like this: (see attachment)

The problem is, when the supply Voltage drops under a certain amount (around 6.8V) the Voltage regulator also drops under 5V. Now I would like to have some kind of "low-voltage cut off switch", which disconnects the USB when the supply voltage drops under 6.8V.

I tried to google it or come up with some own ideas, but everything I found was not really what I was looking for. Does anybody has some idea how to fix my problem or point me in some direction?

Thanks a lot

 

You might consider a simple blocking diode if you need to avoid the reverse voltage problem. If you use a Schottky, it'll lose <0.5V. But I think almost any "smart" device you connect will simply stop using the supply if the USB voltage sags below a threshold. Don't quote me on that.

Consider using an LM3914 for your voltage bargraph.

Using a linear voltage regulator like the 7805 in a solar application is a problem, since it is wastes such a high percentage of your precious power.

 

You may wish to Google "low dropout regulator."

 

I think a look at the I-V curve of the panel would be worthwhile also.

 

You almost have the solution in your schematic.
By using a zener diode for 6.8V connect the anode to a 1K to ground and the gate of an N-channel enhancement MOSFET. The source is connected to the solar panel supply and the drain connected to the voltage regulator input. Oh no, you just lost the use of 2 of your LEDs.

PS: Wait, you can put it after the LEDs so that only the USB connector is turned off.

 

@wayneh: i totally forgot about the blocking diode and, yes, the LM3914 looks interesting for my bargraph . maybe i'll order one and see how i can include it.

@ErnieM: Thanks for the tip. I'll google it

@LDC3: Do you mean like this: (see attachement) I couldn't find a 6.8V zener diode. I just put a diode with a voltage drop of 0.7V in series with the 6.2V zener diode, so it sums up to 6.9V. Is it possible to do it like this?

I also added a switch for the LEDs, so I can just switch them on when adjusting the panel and then switch them off again.

Thanks again for all the replies

 

I posted a blog entry a while back about solar array IV curves and how to design your circuit around them. It's important to know your IV curve when designing a circuit like this. Check out my blog on this site for more info.

I think you're missing a npn transistor driving what should be a logic level p-channel FET and a couple resistors in your latest schematic. I'm thinking something a bit more like what I have attached should work. There's maybe a few other games I'd play with LED placement and such to try to keep efficiency up - but you probably don't care about that.

A blocking diode is not required - it just eats efficiency, and makes it more difficult for your regulator to regulate. Between the FET switch and the regulator - I find it darn near impossible for you to reverse bias your SA.

Good Luck!

 

@LDC3: Do you mean like this: (see attachement) I couldn't find a 6.8V zener diode. I just put a diode with a voltage drop of 0.7V in series with the 6.2V zener diode, so it sums up to 6.9V. Is it possible to do it like this?

I also added a switch for the LEDs, so I can just switch them on when adjusting the panel and then switch them off again.

The connection should be the other side of R11, otherwise the gate is always at ground (the MOSFET conducts when there is a voltage applied). The MOSFET looks to be excessive since the 7805 is 5V and 1A (but if it is cheap, then use it).
Also the capacitor should be as close to the voltage regulator output as possible, so you should move it in the schematic (it should also always be connected to the voltage regulator).

 

I posted a blog entry a while back about solar array IV curves and how to design your circuit around them. It's important to know your IV curve when designing a circuit like this. Check out my blog on this site for more info.

I think you're missing a npn transistor driving what should be a logic level p-channel FET and a couple resistors in your latest schematic. I'm thinking something a bit more like what I have attached should work. There's maybe a few other games I'd play with LED placement and such to try to keep efficiency up - but you probably don't care about that.

A blocking diode is not required - it just eats efficiency, and makes it more difficult for your regulator to regulate. Between the FET switch and the regulator - I find it darn near impossible for you to reverse bias your SA.

Good Luck!

You actually don't need the resistor between the FET and the npn since there is no current through the gate of the FET.

 

A blocking diode is not required - it just eats efficiency, and makes it more difficult for your regulator to regulate.

My thinking in suggesting the blocking diode it was that the regulator might then be eliminated, but I failed to elaborate on how to do that.

I think a current dumping arrangement regulated to start dumping at, say, 5.2V, would be more efficient since it would totally be out of the way when the USB port is drawing lots of charge current, which brings the voltage down naturally.

See the dump circuit here for example. Does nothing until the threshold voltage is exceeded, then send the excess current through a shunt. I think this would work well here, since the excess current is likely to be quite minimal.

 

Thank you so much for all your suggestions. Unfortunately I don't understand all of them, but I try my best .

Here is what I came up with till now: (see attachment).

Would a p-channel MOSFET, IRF9510, 4A ,100V be OK? (http://www.vishay.com/docs/91072/91072.pdf) And are the resistor values also OK?

@tindel: I'll have a look at your blog, but unfortunately I can't find any datasheet of my solar panel

@wayneh: I guess I need a little bit more time or explanation to understand the circuit you posted.

Thanks a lot for your patience

 

@wayneh: I guess I need a little bit more time or explanation to understand the circuit you posted.

In that circuit, ±S are the solar panel leads, and ±B are the battery poles. D1 is the traditional blocking diode. D2 is a ~5V zener diode that conducts nothing to the base of Q1 unless the battery voltage (a 4V SLA) reaches the zener voltage. At that point, a small current results in a voltage on the base of Q1, controlled somewhat by R2 (560Ω) and R3 (1kΩ). The transistor conducts through itself and R1, dissipating heat. It only has to dissipate enough current to draw the panel voltage down from an open circuit voltage of maybe 9V, down to ~5.6 (5V plus the blocking diode drop). That's probably less than half of the short-circuit current rating.

 

Thanks a lot for this precise explanation. I guess I got it pretty much, it makes sense and I guess I'll try it out .

The only thing I'm not sure about is the purpose of R3 and I'm pretty sure there is one .
I'm just thinking that I used the transistors in the same way for my bargraph LEDs, but without any resistor connected from the base to ground. And it worked.

Thanks

 

I was wondering that too and I don't really have an answer. It makes sure the base goes low when the zener is not conducting, and that need may depend on the transistor being used. It may also be used to force the zener current to be a bit higher before the transistor will switch.

 

You actually don't need the resistor between the FET and the npn since there is no current through the gate of the FET.

Well, yes and no - you should almost always place a small resistor on the gate of your power FETs to limit turn-on currents (100-500ohm, usually). The gate-source connection is a capacitor (mostly). In this configuration you basically have a short to ground at initial turn-on which can cause oscillations if the current is not limited. This does slow your transistor switch speed, but to not have a gate resistor on a power fet can lead to many problems - especially when a control loop is involved (the regulator). I should have probably mentioned this in my first post - and forgot.

You can get away without the resistor - but a small-signal analysis should be preformed to verify adequate gain and phase margin.

You might be able to get away without the resistor here because you have to have just enough power just to turn on the FET anyway - which means you will charge the FET slowly.


Elokuu - you don't need a datasheet - you need some resistors and the sun to get an idea of the IV curve - besides - even if you do know the exact IV curve, it's going to vary a lot anyway with intensity and temperature. Without a thermal chamber you probably won't be able to know exactly what it will be like in all conditions - but you should look at your worst-case cases - and get a pretty good idea of what you will see.


wayneh - interesting circuit - I have to think about it a bit - I understand the operation - in fact I've been analyzing a similiar circuit at work - but I think my confusion is with the knee of the zener. If I understand correctly - the knee varies with zener voltage. I was told by a senior engineer that zeners above ~6.4V have a sharper knee over temperature due to the physics of how the zener works (avalanche currents?) than lower voltage zeners do. I do seem to recall something to this effect in my solid-state class - but the details are fuzzy. I guess I need to get a few zeners and run some IV curves.

At work we are required to have base-emitter or gate-source resistor to ensure if something else fails open (D2/R2) the transistor will fail closed. Other than that - I don't see why you'd need R3 either.

 

I don't see why you'd need R3 either.

My guess is that it's just a tweak to achieve the right threshold voltage with the given components. It probably raises the threshold a few tenths of a volt, instead of using a different zener I guess.

 

Hi Elokuu

I have a few suggestions to improve your design. I'll post them separately. Here's the first:

78xx regulators are definitely wasteful for this application. LDO regulators would be an improvement. wayneh's suggested shunt regulator seems (to me) to be the best approach for your application. You could probably find a clever point in this regulator circuit to control a shutoff FET when the source voltage drops below 5V (that's when the shunt regulator would stop shunting, right?).

 

For reverse polarity protection I've been using a FET configured as an ideal diode instead of the usual series diode. That is: source to load, drain to power terminal, gate to opposite power rail with a resistor between gate and rail for gate protection. Yes, the FET is connected backwards, but this solution addresses a very backward situation! There is negligible voltage drop when operating normally, and any reversed voltage is blocked.
http://chasingtrons.com/main/2010/11/9/transistor-shunt-voltage-regulator.html or http://electronicdesign.com/power/fet-supplies-low-voltage-reverse-polarity-protection.

 

There's a fundamental problem with 'simplistic' undervoltage shutoff designs. When the undervoltage condition is sensed, they simply disconnect the load from the power source. In most cases, the power source will 'recover' due to internal resistance and the decreased current draw (a solar cell certainly behaves like this). This causes the undervoltage monitor to turn on... You would end up with oscillation. You will probably want a latching turn-off that stays off the first time undervoltage is sensed. Check out: http://danyk.cz/p_ochr_en.html

The key to the latching behaviour is that the sensing point is downstream from the switch that controls the power. This creates positive feedback which insures stable shutoff once the control action has started. It requires some kind of manual (or other) reset method. I've used a capacitor in place of the momentary switch in the above design. This enforces a reset on power up (works in simulation! ), but still implies manual action. In your application a USB (re)connection would be an ideal reset event. ... or maybe that new switch you added to illuminate the LEDs...

 

There's a fundamental problem with 'simplistic' undervoltage shutoff designs.

Does the USB specification deal with this? I mean, if every device the OP might charge with his device will be smart and disconnect itself when it sees low voltage on the USB host, maybe the OP doesn't need a low-voltage shutoff at all.