I'm using LTC6268-10 to build a ~200MHz TIA (Transimpedance amplifier)
Datasheet: https://www.analog.com/media/en/technical-documentation/data-sheets/626810f.pdf

Here is the schematic:


The frequency response I get:



I expect the bandwidth to only roll off at 250MHz, why does it fall to -3dB at 50MHz and then stays flat then starts rolling of at 200MHz is a mystery I am not able to solver for along time. Any help would be appreciated.

Things I have tried: Changing the photodiode, scrubbing the heck out of the PCB to remove flux, using RF caps and resistors, followed layout guideline as specified in the datasheet.
I see a change only when photodiode is changed, but what happens is the -3dB at 50MHz remains and the second roll off changes according to the bandwidth for photodiode's capacitance.


EDIT: Attaching the ltspice asc file.

 

It's not a simple question to answer.
Can you simulate with LTspice?
Did you get the design from a textbook?

 

Look at the data sheets! The phase shift comes into play a bit before 50 MHZ! so yourfeedback effect comes in to play. So you will need to compensate for that.

 

Look at the data sheets! The phase shift comes into play a bit before 50 MHZ! so yourfeedback effect comes in to play. So you will need to compensate for that.

I do not understand, can you elaborate? Thanks

 

It's not a simple question to answer.
Can you simulate with LTspice?
Did you get the design from a textbook?

Hi, the design is the standard way of building a high bandwidth transimpedance amplifier using opamps. I can simulate the circuit in LTspice, just can't simulate the measured frequency response.

 

hi aagum,
Please post your LTSpice asc file, version of the circuit.
E

 

hi aagum,
Please post your LTSpice asc file, version of the circuit.
E

Hi I have added the asc file.

 

Hi aag,
Is the circuit mounted on a PCB? , I suspect a external circuit build layout is causing the 50MHz problem.
Do you have a photo shot of the project to post?
E

 

Hi aag,
Is the circuit mounted on a PCB? , I suspect a external circuit build layout is causing the 50MHz problem.
Do you have a photo shot of the project to post?
E

Hi, yes it is on a PCB, I cannot post a snapshot of the PCB, I can post the layout image.
Top layer, I have voided all planes below the input path to the opamp.
C29 and R20 are the feedbackcap and resistor.
EDIT: C29 is not populated
U7 is the opamp
R28 is 50 ohms series termination
C25 is DNP
R29 is 0 ohms
J23 is RF connector

 

Did you read the chapter about "Achieving Higher Bandwidth with Higher Gain TIAs" in the datasheet? According to this, C29 and additional stray capacitance might reduce your bandwith.

 

Did you read the chapter about "Achieving Higher Bandwidth with Higher Gain TIAs" in the datasheet? According to this, C29 and additional stray capacitance might reduce your bandwith.

Hi, C29 is not populated. I am aware of how feedback capacitor changes the bandwidth, I am more interested in how the frequency response falls by 3dB at 50MHz and then stays flat before rolling off at the intended ~200MHz frequency point.

 

In response to the much earlier challenge, the gain versus frequency graph shows a gain dropoff around 50 MHz. But you need to go far into the data sheet to see that. It does not stand out, you need to lookclosely to notice it.

 

In response to the much earlier challenge, the gain versus frequency graph shows a gain dropoff around 50 MHz. But you need to go far into the data sheet to see that. It does not stand out, you need to lookclosely to notice it.

Hi, are you talking about this?

But it is just a 1dB drop in gain, while I see 3dB.

 

hi aag,
The closest approximation I can see in the AC response plot is by adding some onboard very low L/C values.
My conclusion is that the onboard track L/C values are the cause of the problem.

E

 

hi aag,
The closest approximation I can see in the AC response plot is by adding some onboard very low L/C values.
My conclusion is that the onboard track L/C values are the cause of the problem.

E
View attachment 365505

Hi, thank you for the reply, the 10Meg is supposed to be photodiode's internal resistance, so adding board parasitics before that is not the correct representaion (unless we are modelling the bondwire inductance of the photodiode, however bond wire inductance cannot be 0.5uH, it will be much lower).

With that being said, the trace length between photodiode output and Cf is 1.52mm, length between Cf and Rf is 1.27mm and length between Rf and opamp input is 1.32mm, and the width of the trace is 0.254mm, refer to layout screenshot for visualizing.

These sorts of dimensions cannot cause an inductance of 0.5uH, and note that all planes beneath this trace have been voided to avoid parasitic capacitance so 1pF capacitance is also unlikely.

 

In response to the much earlier challenge, the gain versus frequency graph shows a gain dropoff around 50 MHz. But you need to go far into the data sheet to see that. It does not stand out, you need to lookclosely to notice it.

Hi, can you point me towards the right direction? I am not able to find anything in the datasheet that would indicate a gain drop by 3dB at 50MHz

 

hi aag,
I agree with your statement, I also do not see any indication on the d/s regarding the -3dB dip @ 50MHz.
I still suspect the cause is located near the input side of the OPA circuitry?

Is it possible to double-check the actual claimed performance of the OPA in the 50MHz region, say by setting up a simple test rig for the OPA?

E

 

hi aag,
I agree with your statement, I also do not see any indication on the d/s regarding the -3dB dip @ 50MHz.
I still suspect the cause is located near the input side of the OPA circuitry?

Is it possible to double-check the actual claimed performance of the OPA in the 50MHz region, say by setting up a simple test rig for the OPA?

E

Thanks, I will do this and update.