Greetings,
I have been using IXFX180N25T for 3phase Induction motor controller design. The design includes 8 mosfets parallel together. I used a series gate resistor of 1ohm for each individual mosfet after current Booster circuit. Each mosfet has 10K pull down and ceramic cap of 10nf at Gate-source.
Every time one mosfet of high side leg is getting burned, i have provided dead band of 5microsec.
The circuit is mounted on heat sink.I can see some unwanted triggering happening in mosfet.
There is No gate ringing present at No load.
The whole circuits works fine when am using infenion AUIRFP4568.
Kindly let me know if there are some suggestions.

 

#PowerElectronics#ev#Mosfet#Startup
V/F algorithim with 100Hz and with 50%voltage amplitude.
When supplied by a voltage of 40Volts its drawing a current of 23A dc and ac out was around 300A constant.The same conditions with Infenion mosfet its drawing intially 200A ac and once wheel starts rotating its taking around 70A ac.

 

1,170 Watts = 300 Amps x 300 Amps x 13 milliohms

What is the maximum amount of time that one MOSFET can dissipate 1,170 Watts before it overheats?

Clearly, there is a differencve between the two MOSFETS.
Did you compare the two datasheets to see what the difference is?

 

One mosfet has capability of conducting 160A @ 70 deg. I was doing later test with 3 Mosfets in parallel.
Yes the comparison inference i found was the gate charge is more for IXYS mos, so i decreased gate resistance and the Drain current pushed in was inside the limits.
Is there any chance that only one mosfet among the 3 paralled will only conduct. I checked the gate pulses to all 3 it was perfectly fine.
The heat sink provided in sufficently air cooled with fins.

I have earlier connected individual Tvs diode of 15v voltage gate-source of mosfet and later replaced it by Ceramic cap of 10NF

The PWM freq is 10Khz

Datasheet of IXYs mos: https://datasheet.octopart.com/IXFX180N25T-IXYS-datasheet-12510223.pdf

datasheet of Infenion : https://www.mouser.in/datasheet/2/196/auirfp4568-1225230.pdf

 

Each mosfet has 10K pull down and ceramic cap of 10nf at Gate-source.

If a mosfet gate is basically a capacitor, that takes a certain amount of time to charge, why would you then add another capacitor to add to the turn on time? I don't understand this and haven't seen it before.

 

One of the problems with MOSFETs is the parasitic turn-on (self-turn-on) phenomenon caused by
their drain-gate capacitance. Upon turn-off, a sharp dv/dt develops between the source and the drain
of a MOSFET. The resulting current flows to the gate via the drain-gate capacitance. As a result, a
voltage drop that occurs across the gate resistor lifts the gate voltage. This current is calculated as:
i DG = C gd ・dv DS / dt
(1) Adding a capacitor between the gate and source terminals
The capacitor inserted between the gate and source terminals absorbs the drain-gate current
caused by dv/dt.Since the gate-source capacitor is connected in
parallel with C gs inside the MOSFET, the gate charge increases. If the gate voltage is fixed, you can
keep the switching speed of the MOSFET unchanged by changing the gate resistor value, but this
increases the drive power consumed.

According to Toshiba Application note : https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwjak_fnhrLiAhU78HMBHeE9BNsQFjAAegQIAxAC&url=https://toshiba.semicon-storage.com/info/docget.jsp?did=59460&usg=AOvVaw3gU3dNaapNcjGpSTQ0hDvO
And i have seen RC filter for Gate in SEVCON Motor controller. But am not sure whether Adding ceramic cap instead of TVS diode helped in any way.

I was facing unwanted triggering of mosfet,now i find out even the dead band for gate of mosfet was there, there was still Vds cross over when transition from high side and low side mosfets happens.
But when i check the gate pulses at Mosfet gate,there i can see 5us deadband but not in Vds signal of same leg.It overlaps like for like 50ns.
And this happens even without connecting any load.
So shud i increase dead band more or try reducing gate resistance even lesser?

 

One of the problems with MOSFETs is the parasitic turn-on (self-turn-on) phenomenon caused by
their drain-gate capacitance. Upon turn-off, a sharp dv/dt develops between the source and the drain
of a MOSFET. The resulting current flows to the gate via the drain-gate capacitance. As a result, a
voltage drop that occurs across the gate resistor lifts the gate voltage. This current is calculated as:
i DG = C gd ・dv DS / dt
(1) Adding a capacitor between the gate and source terminals
The capacitor inserted between the gate and source terminals absorbs the drain-gate current
caused by dv/dt.Since the gate-source capacitor is connected in
parallel with C gs inside the MOSFET, the gate charge increases. If the gate voltage is fixed, you can
keep the switching speed of the MOSFET unchanged by changing the gate resistor value, but this
increases the drive power consumed.

According to Toshiba Application note : https://www.google.com/url?sa=t&rct=j&q=&esrc=s&source=web&cd=1&ved=2ahUKEwjak_fnhrLiAhU78HMBHeE9BNsQFjAAegQIAxAC&url=https://toshiba.semicon-storage.com/info/docget.jsp?did=59460&usg=AOvVaw3gU3dNaapNcjGpSTQ0hDvO
And i have seen RC filter for Gate in SEVCON Motor controller. But am not sure whether Adding ceramic cap instead of TVS diode helped in any way.

I was facing unwanted triggering of mosfet,now i find out even the dead band for gate of mosfet was there, there was still Vds cross over when transition from high side and low side mosfets happens.
But when i check the gate pulses at Mosfet gate,there i can see 5us deadband but not in Vds signal of same leg.It overlaps like for like 50ns.
And this happens even without connecting any load.
So shud i increase dead band more or try reducing gate resistance even lesser?

Dead band.

 

Greetings,
I have been using IXFX180N25T for 3phase Induction motor controller design. The design includes 8 mosfets parallel together. I used a series gate resistor of 1ohm for each individual mosfet after current Booster circuit. Each mosfet has 10K pull down and ceramic cap of 10nf at Gate-source.
Every time one mosfet of high side leg is getting burned, i have provided dead band of 5microsec.
The circuit is mounted on heat sink.I can see some unwanted triggering happening in mosfet.
There is No gate ringing present at No load.
The whole circuits works fine when am using infenion AUIRFP4568.
Kindly let me know if there are some suggestions.

What driver are you using?

 

What driver are you using?

1EDI60N12AF infenion driver ic.
and i have Current booster followed NPN PNP Transistor totem pole configuration.

 

[QU
(1) Adding a capacitor between the gate and source terminals
The capacitor inserted between the gate and source terminals absorbs the drain-gate current
caused by dv/dt.Since the gate-source capacitor is connected in
parallel with C gs inside the MOSFET, the gate charge increases. If the gate voltage is fixed, you can
keep the switching speed of the MOSFET unchanged by changing the gate resistor value, but this
increases the drive power consumed.
OTE="shortbus, post: 1395313, member: 61844"]If a mosfet gate is basically a capacitor, that takes a certain amount of time to charge, why would you then add another capacitor to add to the turn on time? I don't understand this and haven't seen it before.[/QUOTE]

 

I have given a dead band of 5us now. One more doubt am having is At the time when both mosfets of one leg are off what is voltage of Vds of mosfets at that moment.
At the Dead band period Iam getting Vds of both mosfets as 0 voltage. Does that mean both Mosfets are conducting at that time?

 

Vds of high side and low side.
Yellow is High side.
Green is Low side.
For 50ns, Does it mean both are cross conducting?

 

1EDI60N12AF infenion driver ic.
and i have Current booster followed NPN PNP Transistor totem pole configuration.

Maybe you can post at least a block diagram of your circuit. It's not clear to me right now how the gate drain capacitance can turn on the top FET. It would also help to see how your drivers are connected. Eight drivers? eight push pull drivers?

 

Maybe you can post at least a block diagram of your circuit. It's not clear to me right now how the gate drain capacitance can turn on the top FET. It would also help to see how your drivers are connected. Eight drivers? eight push pull drivers?

above is the schematic.