So here is the function and my attempt:




Where the ' annotation means complement and Q2 is the most significant bit and Q0 the least significant bit.

I'm also trying to implement the same function but this time using only one 1*2 decoder but without much sucess. If the only entry of the decoder is Q2, pretty much most of the circuit is just using and's and or's gates without really much of the actual decoder.

 

So here is the function and my attempt:

View attachment 256934


Where the ' annotation means complement and Q2 is the most significant bit and Q0 the least significant bit.

I'm also trying to implement the same function but this time using only one 1*2 decoder but without much sucess. If the only entry of the decoder is Q2, pretty much most of the circuit is just using and's and or's gates without really much of the actual decoder.

I can't make sense of that diagram.

How many inputs does this have?

How many outputs?

Can you just list a table of every possible input and the desired output for each case?

 

It looks like a Karnaugh map to me, with three inputs and one output.
By inspection, if we let the "don't care" state be zero, then the output is the inverse of Q1 except for when Q0 and Q2 are both 1.
Is it essential to use the 2:4 decoder?