I need bounce in my Tina circuit.

Thread Starter

fmrPIC

Joined Nov 11, 2016
15
I have an FPGA generating a 5MHz square wave at 3.3v being received by a register/counter. At the transitions, I see bounce. It is large enough that my data logger sees extra transitions.
My goal is to use a resistor and cap to clean the transitions. I therefore want to use Tina to mimic the ~50-100 MHz bounce over a 5MHz signal and fix it. I can then pick my R and C, check my circuit, and then fabricate a circuit. How do I get my Tina square wave circuit to bounce at the transitions?
 

crutschow

Joined Mar 14, 2008
23,314
You need to add stray capacitance and inductance to the circuit.

What is the distance of the signal from the FPGA to the data logger.
What type of line are you using to carry the signal?

Sounds like you need a properly terminated. transmission line between the two.
 

Thread Starter

fmrPIC

Joined Nov 11, 2016
15
I want to know how to mimic the noise in Tina so I can remove the noise by adding C and L to the circuit and use that info to design a footprint on a PCB.
 

djsfantasi

Joined Apr 11, 2010
5,585
Can’t you use the problematic FPGA circuit square wave as an input to your test circuit? You need not duplicate the entire system... just the portion that creates the bounce? Why create another circuit to mimic the one that you have, when you could use a portion of the problematic circuit?

I’ve done that for microprocessor systems I’ve built. I use almost all of the original circuit as input to a system under development.
 

crutschow

Joined Mar 14, 2008
23,314
I want to know how to mimic the noise in Tina so I can remove the noise by adding C and L to the circuit and use that info to design a footprint on a PCB.
Yes, we understand that.
But it would help if you answer my questions in Post #2.

The ringing can likely be minimized by placing a resistor (say 80-100Ω) in series with the output of the FPGA.
You'd need to experiment to determine the best value.
 

Thread Starter

fmrPIC

Joined Nov 11, 2016
15
Here is my plan. I have 8 lines I want to potentially clean. I have a 25 pin ribbon cable that connects the FPGA to the register. The others are grounds or DC and appear to be cleaning the signals. I will have a PCB made with three 1206 footprints on each of the 8 lines and connector footprints for the ribbon cables. One 1206 footprint in series and two more that are in series and go to ground. With those three, I hope I can either resistor load or RC load or change impedance with a series resistor and clean the signals. There should be a magic combination as a fix.
 

crutschow

Joined Mar 14, 2008
23,314
There should be a magic combination as a fix.
Possibly.
But you are unlikely to determine than with a simulation unless you can accurately model all the parasitics in your system, which is rather difficult.

I would start with adding a resistor in series and see if you can reduce the ringing to a tolerable level with that.
Where are the series pads located with respect to the FPGA output?
The should be near its output.
 

Thread Starter

fmrPIC

Joined Nov 11, 2016
15
It will be as close as I can which is about 3 inches. There is a 30 inch ribbon cable currently. I am adding a 2inch ribbon cable and a 1.5" x 1.5" PCB with connectors. I am replacing an existing FPGA. They are using 6xx series components with a lot of silk screening making it difficult for me to trace a run. My goal today is to trace a run to see what they are using and finish this PCB jumper. I do see several R to C to GNDs on the board I am replacing. My FPGA is actually a Development Board. I thought my DB's GPIO pins were buffered to give clean signals but these are not. I will keep you posted.
 
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