Hello,

I am new to VHDL and am trying to adapt code from https://github.com/skiselev/tiny_z80/tree/master/CPLD
to implement memory paging registers for a Z80 board (with a Xilinx CPLD XC9572XL-10VQ64C).
Paging registers should provide 4 banks of 16Kb (in Z80 address space), mapping 512Kb, should be writable and readable back.
(similar to how it is described in https://www.smbaker.com/16-megabytes-of-ram-in-a-heathkit-h8-vintage-computer).

For now I am stuck as it seems that the values are not written or retained by the registers.

The simulation in Xilinx iSim shows that correct values are stored and read from the register (with test bench for the "page_reg_4x6_lpm.vhd").
This does not match with the physical CPLD.


For now I cannot get the value written in any of the paging registers back, the PA is read as zeros.
When reading D6 holds correct value for PAGE_ENA (written to and read from PAGE_ENA_FF flip flop), lower bits are always 0.

In asm
out (78h),2ah ; write to the first paging register
in a,(78h) ; read the value back, but always getting only PAGE_ENA and zeros for the rest


The use of the paging register (A_HI are the A14, A15 bits of address):

rdaddress <= A(1 downto 0) when PAGE_RD = '1' else A_HI;

-- Page register
PAGE_REG : page_reg_4x6_lpm port map(CLK => CPU_CLK, RSTn => RSTn,
data => D(5 downto 0),
-- rdaddress => A_HI,
rdaddress => rdaddress,
wraddress => A(1 downto 0),
wren => PAGE_WR,
q => PA);

...
D(6) <= PAGE_ENA when PAGE_RD = '1' else 'Z'; -- this comes back as expected
D(5 downto 0) <= PA(19 downto 14) when PAGE_RD = '1' else (others => 'Z'); -- always zeros

Is it correct to hold register values in the page_reg_4x6_lpm itself like
SIGNAL sub_wire0 : STD_LOGIC_VECTOR (5 DOWNTO 0);
or should they be moved to tinyz80 entity for them to be preserved (maybe I misunderstand the basics)?

 

Your basic problem , is the lpm part is an altera special
And this is a old xilinx part you have chosen,

 

Thanks for the response. The parts are old, true.

I tried to remove everything altera specific and use only standard vhdl in the register, probably did notunderstood something from the original (got it on the xilinx chip). lpm stayed in the name though.

 

Thanks for the response. The parts are old, true.

I tried to remove everything altera specific and use only standard vhdl in the register, probably did notunderstood something from the original (got it on the xilinx chip). lpm stayed in the name though.

That's the point
You have taken out the read process of the ram,
Bottom line you need to takecstep back and understand what you want the code to do,
Something like this problem,
The way to approach is to take the original code in the orrigonal tools an simulate the he'll out of it till you understand what it's doing,
Then still in the orrigonal tools, take out the altera coded and put it generic vhdl, and re run all those tests to prove it still eorks same,
Only then, copy test bench and code into new tools and repeate tests,
Once you get better you will recognise shirt cuts, but the above is still the route I start with,