xc9572xl

Hello, I am new to VHDL and am trying to adapt code from https://github.com/skiselev/tiny_z80/tree/master/CPLD to implement memory paging registers for a Z80 board (with a Xilinx CPLD XC9572XL-10VQ64C). Paging registers should provide 4 banks of 16Kb (in Z80 address space), mapping 512Kb...