Hi GF,
Change the .tran to this image, add the 1V AC to the V1 source details.

Add a Node label as Vin and one for Vout, using the F4 key.

Ask if you have a problem.
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View attachment 294977View attachment 294979View attachment 294980

Thanks for the explanation. Just to clarify, I need to measure my low and high cut-off frequencies at 3dB?

 

Thanks for the explanation. Just to clarify, I need to measure my low and high cut-off frequencies at 3dB?

Hi GF,
Follow the instructions I posted, and then post an image of the LTSpice plot.
We can compare the 3dB points on your amplifier circuit.

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This is the AC analysis of your circuit, it is not within the required specification.

 

If I switch the pnp to be the correct way around does the resistor and output still stay above?

It does not matter if it is an NPN or PNP transistor.
Think circuit topology.
If the load is on the collector then it is a common emitter amplifier.
If the load is on the emitter then it is an emitter follower.

One of the two has 180° phase change.

 

Hi GF,
Follow the instructions I posted, and then post an image of the LTSpice plot.
We can compare the 3dB points on your amplifier circuit.

E
This is the AC analysis of your circuit, it is not within the required specification.

Here is the LTSpice plot.

 

It does not matter if it is an NPN or PNP transistor.
Think circuit topology.
If the load is on the collector then it is a common emitter amplifier.
If the load is on the emitter then it is an emitter follower.

One of the two has 180° phase change.

Okay, thanks I understand.

 

The powerful emitter-follower PNP transistor pushes the output negative but the voltage divider caused by the 2k emitter resistor pulls it less positive.
It might even be distortion where the top of the waveform is squashed a little. Opamps have push-pull transistors at the output to avoid that king of distortion.

I noticed that the second stage could be re-biased to allow more peak symmetrical voltage swing producing some "headroom":

 

hi agu,
It would be a good idea if you read and followed the TS required specification.
Your posts are misleading.

Clip:
 The input signal shall be a 200 mV peak-to-peak sine wave generated by a standard laboratory signal generator
 The midband gain of the amplifier shall be 50 V/V
 The output signal of the amplifier shall be in phase with the input signal (not inverted)
 The low 3 dB cut-off frequency shall be 20 Hz
 The high 3 dB cut-off frequency shall be 18 kHz
 The supply voltage shall be ±15 V
 The input and output shall be ac coupled to the amplifier
 The BJTs used shall be KSP2222A (NPN) and KSP2907A (PNP)

 

Earlier, I showed that the emitter-follower emitter resistor had a resistance that was too high for a 5V peak output.
Recently I showed that if the second transistor has its biasing corrected then the max output level can be almost 3dB higher.
The cutoff frequency capacitors have not been calculated yet.

 

Hi agu,
I think we all know if you deliberately over drive an amplifier designed for a 100mV 1kHz sine input, for a gain of 50, by using a 180mV and 200mV it will clip.

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Which capacitors should be responsible for the low cut-off and which should be responsible for the high cut-off?

 

Which capacitors should be responsible for the low cut-off and which should be responsible for the high cut-off?

You don’t have any capacitors which will limit the high frequency response.

 

You don’t have any capacitors which will limit the high frequency response.

So I should put capacitors in parallel with the emitter resistance to get a high cut-off?

 

Which capacitors should be responsible for the low cut-off and which should be responsible for the high cut-off

Hi GF,
Looking at your AC plot shows the lower 3dB point of 20Hz is 'close'
Where, in the circuit, do you consider would be a good point to add the 18kHz limit components and their type.
I cannot help too much as this is homework.
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So I should put capacitors in parallel with the emitter resistance to get a high cut-off?
No.

 

So I should put capacitors in parallel with the emitter resistance to get a high cut-off?

Think of the gain equation for each stage. Reducing which element would reduce the gain?

For the low frequency cutoff, it is common practice to use just one of the three possible capacitors to set the cutoff frequency, and set the other two so low that they don’t have any effect.

 

Should it be capacitors from the base of the transistor to the output? Like this:

 

Does this look correct?

 

Should it be capacitors from the base of the transistor to the output? Like this:
View attachment 295034

It wasn‘t what I was thinking of, but it works.
Again, you only need to filter on ONE stage.

 

It wasn‘t what I was thinking of, but it works.
Again, you only need to filter on ONE stage.

Okay thank you I will try to improve it now.

 

Hi agu,
I think we all know if you deliberately over drive an amplifier designed for a 100mV 1kHz sine input, for a gain of 50, by using a 180mV and 200mV it will clip.

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Since the second transistor was biased wrong, the amplifier needed a 30V supply (!) to avoid clipping on its 10V output
All amplifiers sound better when they have extra headroom. When the drum beat is clipping then most people hear that something is wrong but they do not know it is compression caused by clipping.

 

hi agu,
The TS's circuit in post #57 will tolerate a 10% input over drive [110mVppk] before it clips at 11.7Vppk [ 10Vppk is the spec requirement]

So how do you figure it need a 30V supply.???
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