When I use R3=4k and R4=280 I get very close to 10 gain

 

Should I split the gain between all three stages or just the first two? What would you recommend?

 

Should I split the gain between all three stages or just the first two? What would you recommend?

A gain of 10 in the first stage and 5 in the second will give you a total gain of 50.
The function of the output stage should be to provide power into the load with a voltage gain of 1.

 

Higher gain in he first stage will give better noise performance.

 

Higher gain in he first stage will give better noise performance.

A higher than 10 gain?

 

Typically, a transistor might have a beta of 100 to 300.
We don’t design a single stage amplifier with that much gain. Instead, we use negative feedback which provides many advantages.

A circuit gain of 10 to 25 is very adequate for your application.

 

Hi MC,
The TS has been given a Gain figure of 50V/V ie: 50, using a 3 stage BJT amp.

The midband gain of the amplifier shall be 50 V/V

E

 

Hi MC,
The TS has been given a Gain figure of 50V/V ie: 50, using a 3 stage BJT amp.

The midband gain of the amplifier shall be 50 V/V

E

Yes. I am suggesting a gain of 10 in the first stage and a gain of 5 in the second.

 

Hi MC.
That's the gain/stage ratio's I am trying to get the TS to design.
The specified BW is limited to 20Hz /18kHz.
No Input or output impedances specified.
E

 

Does this look fine for 50 gain after 2 stages ?

 

The last stage has to be a pnp according to the specifications so this is the design I came up with for a gain of 50.


I now need to get the correct bandwidth freqeuncy. Is that only dependent on the capacitors ?

 

Your PNP transistor is upside down.

 

You have the PNP transistor connected the wrong way round.

 

Think positive current flow.
The arrow on the emitter shows the direction current will flow in a properly biased transistor.

 

Hi F,
It helps if you post your versions of the circuit LTSpice asc file.
Do you know how create to the AC analysis plots for the BW.?
E

 

If I switch the pnp to be the correct way around does the resistor and output still stay above?

 

Hi F,
It helps if you post your versions of the circuit LTSpice asc file.
Do you know how create to the AC analysis plots for the BW.?
E

Here is my file.

No, I am not sure how to do that, do you have anywhere I can go look at how to do it?

 

Hi GF,
Change the .tran to this image, add the 1V AC to the V1 source details.

Add a Node label as Vin and one for Vout, using the F4 key.

Ask if you have a problem.
E

 

Do it like this:

 

Do it like this:

When I do it like that my amplitude to the positive side is less than it is to the negative side. Why does that happen?