# How to design a multistage discrete BJT amplifier

Status
Not open for further replies.

#### GF Oberholzer

Joined May 23, 2023
39
When I use R3=4k and R4=280 I get very close to 10 gain

#### GF Oberholzer

Joined May 23, 2023
39
Should I split the gain between all three stages or just the first two? What would you recommend?

#### MrChips

Joined Oct 2, 2009
30,780
Should I split the gain between all three stages or just the first two? What would you recommend?
A gain of 10 in the first stage and 5 in the second will give you a total gain of 50.
The function of the output stage should be to provide power into the load with a voltage gain of 1.

#### Ian0

Joined Aug 7, 2020
9,765
Higher gain in he first stage will give better noise performance.

#### GF Oberholzer

Joined May 23, 2023
39
Higher gain in he first stage will give better noise performance.
A higher than 10 gain?

#### MrChips

Joined Oct 2, 2009
30,780
Typically, a transistor might have a beta of 100 to 300.
We don’t design a single stage amplifier with that much gain. Instead, we use negative feedback which provides many advantages.

A circuit gain of 10 to 25 is very adequate for your application.

#### ericgibbs

Joined Jan 29, 2010
18,827
Hi MC,
The TS has been given a Gain figure of 50V/V ie: 50, using a 3 stage BJT amp.

The midband gain of the amplifier shall be 50 V/V

E

#### MrChips

Joined Oct 2, 2009
30,780
Hi MC,
The TS has been given a Gain figure of 50V/V ie: 50, using a 3 stage BJT amp.

The midband gain of the amplifier shall be 50 V/V

E
Yes. I am suggesting a gain of 10 in the first stage and a gain of 5 in the second.

#### ericgibbs

Joined Jan 29, 2010
18,827
Hi MC.
That's the gain/stage ratio's I am trying to get the TS to design.
The specified BW is limited to 20Hz /18kHz.
No Input or output impedances specified.
E

#### GF Oberholzer

Joined May 23, 2023
39
Does this look fine for 50 gain after 2 stages ?

#### GF Oberholzer

Joined May 23, 2023
39
The last stage has to be a pnp according to the specifications so this is the design I came up with for a gain of 50.

I now need to get the correct bandwidth freqeuncy. Is that only dependent on the capacitors ?

#### Audioguru again

Joined Oct 21, 2019
6,687
Your PNP transistor is upside down.

#### Ian0

Joined Aug 7, 2020
9,765
You have the PNP transistor connected the wrong way round.

#### MrChips

Joined Oct 2, 2009
30,780
Think positive current flow.
The arrow on the emitter shows the direction current will flow in a properly biased transistor.

#### ericgibbs

Joined Jan 29, 2010
18,827
Hi F,
It helps if you post your versions of the circuit LTSpice asc file.
Do you know how create to the AC analysis plots for the BW.?
E

#### GF Oberholzer

Joined May 23, 2023
39
If I switch the pnp to be the correct way around does the resistor and output still stay above?

#### GF Oberholzer

Joined May 23, 2023
39
Hi F,
It helps if you post your versions of the circuit LTSpice asc file.
Do you know how create to the AC analysis plots for the BW.?
E
Here is my file.

No, I am not sure how to do that, do you have anywhere I can go look at how to do it?

#### Attachments

• 6.4 KB Views: 4

#### ericgibbs

Joined Jan 29, 2010
18,827
Hi GF,
Change the .tran to this image, add the 1V AC to the V1 source details.

Add a Node label as Vin and one for Vout, using the F4 key.

Ask if you have a problem.
E

#### Audioguru again

Joined Oct 21, 2019
6,687
Do it like this:

#### Attachments

• 40.4 KB Views: 10