Greetings!!I did some tests and this is the best result I got... a bandwidth of around 42Khz (compared to the 5.2Khz I had previously with the same schematic but without the second current mirror(MOS M9 and I1)). I saw from the datasheet that the 2N7002 device appears to be in saturation for a VGs=5V and an ID=50mA therefore I opted for the solution in the schematic by creating an additional current mirror with an NMOS device(the mos M9). The only fact is that the open loop system is unstable since at unit gain the phase is approximately 209° (they are unstable for approximately 30° above)... If I introduce the miller capacitance to compensate the system the bandwidth is reduced and I know this... is there some additional technique that allows me to maintain a good bandwidth and maintain a decent phase margin ?? thank you very much!! Attached is the ltspice schematic(AMP_MULTISTAGE) and a screenshot of the test I had previously done with load resistor and nmos cascode bias with Vgs. I saw also that it is possible to implement a common source cascode stage to avoid the miller effect by trying to maintain a center band that has the differential output stage (it is around 1.2Mhz). The problem is that I can't implement a common source stage that gives me optimal gain and at the same time maintains a good center band.
I also tried the option in the photo(WITH BUFFER BETWEEN DIFFERENTIAL AND COMMON SOURCE STAGE) to try to isolate the common source with a buffer avoiding the Miller effect. in this way the common source gain is good (around 80db) and the center band of the differential is also maintained at the output. the only problem is that I also have instability here at open cycle of about 50° above the phase margin, and that's too much...

I also tried the option in the photo(WITH BUFFER BETWEEN DIFFERENTIAL AND COMMON SOURCE STAGE) to try to isolate the common source with a buffer avoiding the Miller effect. in this way the common source gain is good (around 80db) and the center band of the differential is also maintained at the output. the only problem is that I also have instability here at open cycle of about 50° above the phase margin, and that's too much...

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