Facebook
Google
GitHub
Linkedin
not gate?
How should I stop 7 segment for counting? It should be only be counting 0-8.
- Thread starter Tomomi Mei Manalili Reyes
- Start date
How many inputs do you need to decode 9? What is the relationship? NOT, OR, NOR, AND, NAND, XOR, XNOR?
What logic level does the counter need for reset to zero?
2... is it NOR gate? if the 2 input is 0 - the output is 1. if the 2 input is 1 - the output is 0?
Not NOR.
What logic level does the counter require for reset to zero? Which two outputs do you need to decode for 9?
For 9
A - 1
B - 0
C - 0
D - 1
For 8
A - 0
B - 0
C - 0
D - 1
I should 0 the A to became it 8....
A - 1
B - 0
C - 0
D - 1
For 8
A - 0
B - 0
C - 0
D - 1
I should 0 the A to became it 8....
D must be 0 again after it 1
What would happen if you reset the counter when the count was 8? How long would the count stay at 8? Long enough for you to see it?
it will become 0 again and continue its task.
I know this, i just didnt stated it.. Cuz i guess its obvious..
A - 0 1 0 1 0 1 0 1 0
B - 0 0 1 1 0 0 1 1 0
C - 0 0 0 0 1 1 1 1 0
D - 0 0 0 0 0 0 0 0 1
B - 0 0 1 1 0 0 1 1 0
C - 0 0 0 0 1 1 1 1 0
D - 0 0 0 0 0 0 0 0 1
Your counter should display the digits 0-8 for the same amount of time (one clock). If you decode 8 and reset the counter, 8 will only be displayed for the time it takes the clock to propagate through the logic and then reset. That time will be less than a microsecond and you won't be able to "see" the 8 on the display.
Describe what conditions you need to reset the counter at 9.
QA needs to be HIGH
QB needs to be LOW
QC needs to be LOW
QD needs to be HIGH
and the output needs to be ?
Ok, let's use these two tables from the previous posts.
On the left table; to reset the counter to zero, R0 inputs must be R0(1)=H, R0(2)=H. One of the R9 inputs must be L.
So let's make R9(1) and R9(2) Low.
On the right table, at count "9", QA and QD must be H and QB and QC must be L, right?
Now tell me,
1) What logic gate will output a "H" when both inputs are H?
2) What logic gate will output a "H" when both inputs are L?
Then you can connect those two gates like this....
Now do you get the idea? Once you can understand the above circuit logic, we'll tell you how to simplify the above circuit without the 2 black boxes...
Allen
On the left table; to reset the counter to zero, R0 inputs must be R0(1)=H, R0(2)=H. One of the R9 inputs must be L.
So let's make R9(1) and R9(2) Low.
On the right table, at count "9", QA and QD must be H and QB and QC must be L, right?
Now tell me,
1) What logic gate will output a "H" when both inputs are H?
2) What logic gate will output a "H" when both inputs are L?
Then you can connect those two gates like this....
Now do you get the idea? Once you can understand the above circuit logic, we'll tell you how to simplify the above circuit without the 2 black boxes...
Allen
Last edited:
the output is 9. I must low the QA so that the output will be 8?
You're going to let the counter count 0, 1, ..., 7, 8, 9 and reset it as soon as it gets to 9. It will be at 9 so briefly that your eyes won't be able to register a 9 on the display before it gets reset to 0.
i tried the or gate.. and it counting to 0-2.. so, im i getting there?? Thank you for the big info!! 
when i use And and Nand.. 0-5 was the output
2 input of L - output H ------------- And, Or, ExNor
2 input of H - output L ------------- Nand, Nor, ExNor
2 input of H - output L ------------- Nand, Nor, ExNor
You won't need to guess if you describe in words the conditions you want to reset the counter.when i use And and Nand.. 0-5 was the output
You seem to be practicing "design-by-happening", meaning that you try essentially random things will little to no idea what you should expect, but rather just hope that, eventually, something will just happen to do what you want.when i use And and Nand.. 0-5 was the output
