How does the NCP81080 dual gate driver work?

Now I’ve a circuit need used this components but I couldn’t understand it’s operation principal,

Here is datasheet
https://www.onsemi.cn/PowerSolutions/document/NCP81080-D.PDF

It’s means I need two signal HI and LI input
So if I generate square wave duty 50% one of positive another is negative for input.
So I need to delay my signal?
Because in typical timing diagram has fixture 135ns dead time

Another questions is typical application circuit output has resistor and capacitor what it’s means ?
Means one is DC loading on resistor another is AC loading on capacitor? Or RC parallel filter?

Thanks for your help...I study of this circuit several days, but still couldn’t realize this function....

 

If you put a square wave into one input and the same square wave inverted into the other you should get The high side switch and the low side switch switching on their respective MOSFETs 180° out of phase with one-another. Any overlap in you input will (as you noted) be removed and replaced by the 135ns from the dead time circuit.


In this typical application illustration the inductor and capacitor form a low pass filter to remove the AC component of the Pulse Width Modulated voltage from the two MOSFETs , leaving DC or if audio (for example) a signal with a bandpass much lower than the repetition rate of the PWM signal.

 

Welcome to AAC!
If FETs with a large gate capacitance are being driven, the 135nS dead-time may not be enough to prevent some shoot-through. If so, you may need to introduce delay between the Hin and Lin inputs externally.

 

Got it! I’ll try it ~
Thanks for recommend