Does Good Eye Diagram Ensure no error in PRBS Test?

Thread Starter

kyliu

Joined Nov 4, 2021
1
As written in title, just want to ask, does good eye says there is no error in PRBS test? Assume there is no 1 send as 0 or vice versa in TX side, and the line speed is 25.78125Gbps, the voltage swing is max and in prbs test there is still around 10 bit errors every second.
 

MrChips

Joined Oct 2, 2009
34,694
As written in title, just want to ask, does good eye says there is no error in PRBS test? Assume there is no 1 send as 0 or vice versa in TX side, and the line speed is 25.78125Gbps, the voltage swing is max and in prbs test there is still around 10 bit errors every second.
The answer is no. There are other places where errors can be made.
 

Michael42

Joined Apr 20, 2026
5
I’d say no, a “good” eye alone doesn’t mean error free, at ~25.7 Gbps even a clean looking eye can still give you errors, and ~10 bit errors per second is definitely not acceptable for a proper PRBS test, that points to margin issues like jitter, noise, or equalization not being optimal rather than a TX bit flip problem
 

drjohsmith

Joined Dec 13, 2021
1,579
can you share picture of the eye you see please
i assume your grabing the eye using something like the AMD xilinx iBert
i.e inside the receiver chip
How is the data encoded on the link
A good eye should have little verability symbol to symbol
and have good edges , and full max amplitude
your ber is 10 bits in 25,700,000,000 bits ,
youd expect on a good link around 1 in 10^12, i.e. 1 in 1,000,000,000,000
so the link should have other indicator flags
is the pll locked to the constant data stream ?
is the ref clock multiplier locked ?
is the ref clock low jitter ?
is the bert tester your code or an off the shelf / built in tester
 
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