Does a 3-phase phase-locked loop diagram possible for an AC to DC battery charger?

Thread Starter


Joined Sep 5, 2019
Hi there,

In order to achieve unity power factor control, the phase of the AC voltage needs to be obtained. The phase is obtained through a phase-locked loop (PLL).

Take a look for single phase control structure of the PLL ,

For such similar way I want to mention some of 3-phase equations, could you kindly elaborate it more ?

VSa = 1/3*(VSab-VSca);
VSb = 1/3*(VSbc-VSab);
VSc = 1/3*(VSca-VSbc);

VSalpha = 2/3*(VSa - (0.5*VSb) - (0.5*VSc));
VSbeta = 2/3 *(SQRT3_2*VSb - SQRT3_2*VSc);

VSq = VSalpha*COS_theta + VSbeta*SIN_theta;
VSd = -VSalpha*SIN_theta + VSbeta*COS_theta;

VSd_error = (VSd - VSd_ref);

freq_delta += (Kp_PLL*(VSd_error-AC_FREQ_PERR) + Ki_PLL*VSd_error);


p_VSd_error = VSd_error;

if(freq_delta > 5.) freq_delta = 5.;
if(freq_delta < -5.) freq_delta = -5.;

freq = ((AC_FREQ_NORMAL ? 50 : 60) + freq_delta);

freq_filtered = 0.99*freq_filtered + 0.01*freq;

theta += (PI2*freq_filtered*AC_TSW);
AC_TSW= 0.000033

Lets angle theta goes pi to 2*pi.

Kindly discuss logically.

Thread Starter


Joined Sep 5, 2019
Are you working on Power Factor Control?
I have never used a PLL when doing that.
Is this a school project?
No man. This is industrial one.
My one is very smart, kind of full bridge type but at in put and output it has inductor, first one might work as a filter, but output one is kind a of multilevel or mutually coupled. My be for suppressing ripple current .Lets say my input is 3p 380VAC, 60Hz, Main Transformer MTR runs at 20kHz, DC output should be 50-147 v, charging current 100A. Switching frequency is 120kHz, dead time120. Should have CC and CV mode of operation.

I think my system has leading PFC, because it does not have resistive load ( just when I test it with R), lets think battery works like a capacitor. Look at the datasheet of HF IGBT from infenon. I am using 6 pulses but with a different fashion,

I would like to request you at least read this publication attached to this thread.


Thread Starter


Joined Sep 5, 2019
I don't see the need for PFC in a battery charger. Knock yourself out coming up with a solution to a non problem.
At least you have to describe why we dont need PPL or PFC in such case!
Some people said,

a phase lock loop is often used to generate a reference for the PFC stage - on very large rectifiers, >50kVA, the 6 switch bridge is some times used for harmonic cancellation of nearby non-linear loads as well as supplying the 700V bus for the down converter.
Other expert says...
I don't know about all of that but seems to me the PLL
just needs a /3 final stage from which you can get the
three reference edges by logic. Or, you put that /3 logic
outside the PLL and let the PLL lock (say) VSa_div with the
other two (VSb_div, VSc_div) "riding the train".

Checking those other two reference edges against
their real line phases' angles (zero crossings?) might
offer you some line-in phase fault detection
Now look at this diagram implemented by TI DSP.

사본 -Overall-circuit-configuration-of-the-universal-charger-with-the-signals-of-the-control.png

Can you understand which part has reactive element and angular function. d, q both depends on theta.
Yes, my control system also has zero-cross detection but from firmware code it has been ignored. Some library gives you sampling angle table, and you can use it.
The reason why I have arise this question because, most of the research papers deals with L and R comes from AC source, my one has just 1 input inductor

Thread Starter


Joined Sep 5, 2019
Outstanding insight I toast you! Have a drink on me. or two.:)
View attachment 245974
For some reason you wont be able to avoid your foams appeared in your bear glass, you have to drink after a while.
Anyway I got a reasonable answer about this specific topic.

Take a look.

The controller for a three phase PFC or active frontend (AFE) should consider possible unbalanced mains voltages, deviations from symmetrical 3x120° input. A possible scheme locks the PLL to an average phase of mains lines, e.g. by averaging the phase error of alpha and beta component.

The controller should be able to generate assymetrical voltage feedforward and also react on voltage dips and drops.