Hi folks,

I have 3 single-channel gate drivers that drive 3 high-power MOSFETs and I want to implement a protection system so that only one MOSFET is ON in this configuration of 3 MOSFETs, even if the software messed up and turned on 2 MOSFETs simultaneously.
My approach was something like this:

but I am not sure if there is a chip of some sort that can achieve this. Or is there a better approach to this?
Does this approach affect the input PWMs?

Regards,

 

If more than one MOSFET gets a signal, do you care which one is the only one to be on?

 

If more than one MOSFET gets a signal, do you care which one is the only one to be on?

The idea is that only one MOSFET is ON at a time, so in the event of a second MOSFET being turned ON mistakenly, its the gate driver must be disabled at that time..
So the first gate driver to receive the ON signal must turn Disable the 2 other gate drivers...

 

The idea is that only one MOSFET is ON at a time, so in the event of a second MOSFET being turned ON mistakenly, its the gate driver must be disabled at that time..
So the first gate driver to receive the ON signal must turn Disable the 2 other gate drivers...

Okay, so the circuit will need memory (i.e. latch or FF) to remember which signal came first.
The problem is doing this for a PWM signal which is oscillating high and low, so the signal would need to be rectified to give a steady "ON" signal.
Is there a timeframe for how fast the PWM signal switches from one MOSFET to the other?

 

Will you be OK if, when more than one PWM signal is high all MOSFETs are off?
There are many different NOR gates, many come 4 in a package. Two input 1 output.
There is also 3 input and 4 input ..........
1)Connect PWM2 to A, Connect PWM3 to B, Connect the output to EN1. If PWM2=1 or PWM3=1 then EN1=0.
2)Connect PWM1 to A, Connect PWM3 to B, Connect the output to EN2.
3)Connect PWM1 to A, Connect PWM2 to B, Connect the output to EN3.

 

Okay, so the circuit will need memory (i.e. latch or FF) to remember which signal came first.
The problem is doing this for a PWM signal which is oscillating high and low, so the signal would need to be rectified to give a steady "ON" signal.
Is there a timeframe for how fast the PWM signal switches from one MOSFET to the other?

every 80us the signal switches to the next MOSFET.

 

every 80us the signal switches to the next MOSFET.

Okay.
What is the PWM frequency?

 

Will you be OK if, when more than one PWM signal is high all MOSFETs are off?
There are many different NOR gates, many come 4 in a package. Two input 1 output.
There is also 3 input and 4 input ..........
1)Connect PWM2 to A, Connect PWM3 to B, Connect the output to EN1. If PWM2=1 or PWM3=1 then EN1=0.
2)Connect PWM1 to A, Connect PWM3 to B, Connect the output to EN2.
3)Connect PWM1 to A, Connect PWM2 to B, Connect the output to EN3.

View attachment 326054

Thanks for the suggestion ronsimpson,
the SN74HC27DR looks like a good option..i will see if it can work.
but will it affect the PWM signal in terms of PCB routing, since the PWM signals will be routed in and out of the NOR Gates..

 

Okay.
What is the PWM frequency?

the carrier frequency is 50Hz and the minimum on time is 20us for all signals (PWM1-3 respectively).



All signals turned ON at the same time (in simulation).



PS: Signals shouldn't overlap, but since the control algorithm isn't optimized for the MCU to be used to generate the signals, we are expecting some shorts, and to save the SiC MOSFETs and capacitors, we ought to put this protection circuit just in case.

 

How about a 74HC238?
PWM signal to E3, and A0,A1 and A2 select which of the eight outputs it goes to, whilst the others are at 0V.

 

since the PWM signals will be routed in and out of the NOR Gates..

The way I see it, the PWMx lines go directly to the Si8271 with no delay.
There will be some nS delay shutting down the other two Si8271. Normally the other two Si8271s will be low so shutting them down will not affect them.

Please check my work.
If PWM1=high, then Gate Drive 2 & 3 will be turned off. Gate Driver 1= high.
If all PWMs are zero then all Gate Drivers are on and the output = 0.
If PWM1=1 and PWM2=1 then all Gate Drivers = off.

 

Use a decoder to steer a select signal to the desired EN pin.

 

the carrier frequency is 50Hz and the minimum on time is 20us for all signals (PWM1-3 respectively).

Do you mean 50kHz?
20µs is only one period of 50kHz.

 

The idea is that only one MOSFET is ON at a time, so in the event of a second MOSFET being turned ON mistakenly, its the gate driver must be disabled at that time..
So the first gate driver to receive the ON signal must turn Disable the 2 other gate drivers...

This is the tricky part as it requires some sort of memory to remember which was first.
I don't see that in any of the proposed schemes.

 

Has anybody bothered to ask why these requirements even exist ????
What is the application ?
.
.
.

 

Maybe you can place a two small logic mosfets to every gate and drive these two with other inputs:

 

The way I see it, the PWMx lines go directly to the Si8271 with no delay.
There will be some nS delay shutting down the other two Si8271. Normally the other two Si8271s will be low so shutting them down will not affect them.
View attachment 326083
Please check my work.
If PWM1=high, then Gate Drive 2 & 3 will be turned off. Gate Driver 1= high.
If all PWMs are zero then all Gate Drivers are on and the output = 0.
If PWM1=1 and PWM2=1 then all Gate Drivers = off.

it looks like it could work .. but I am a little concerned about 2 things:
1. propagation time, as the Si8271 behaves in about 30ns (VIA to VOA) and it takes 60ns MAX for the device to shut down after a low on EN pin and the 74hc02 takes another 30ns .. so in the event of 2 signals are high simultaneously, they will short even before the other Si8271 gets disabled ...

2. My other concern is PCB layout. Usually, it is recommended to shorten gate signals, which might raise some issues as the ON time in those PWMs gets as small as 20 us.

 

Maybe you can place a two small logic mosfets to every gate and drive these two with other inputs:

View attachment 326104

Thank you for the suggestion
I will try to simulate this .. and see if it works

 

Has anybody bothered to ask why these requirements even exist ????
What is the application ?
.
.
.

The application is an attempt to prototype a packed E-Cell (PEC-9) Inverter.
and this requirement is just a preventive scheme in case the MOSFETs short.

 

2. My other concern is PCB layout. Usually, it is recommended to shorten gate signals, which might raise some issues as the ON time in those PWMs gets as small as 20 us.

The most important part of "shorten gate signals" is the length from Gate driver IC to MOSFET, including the return path. I don't worry much about before the Gate Driver. Do a good job but not critical.
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It has been stated several time that:

How about a 74HC238?
PWM signal to G1, and A0,A1 and A2 select which of the eight outputs it goes to, while the others are at 0V.

Here the "EN" pin is not used on the Gate Driver.
There is only one PWM signal. Two lines select which MOSFET is driven or none "Y3-Y7".
Use HC or AHC or some fast logic.