Hi there,

I am having trouble understanding the output of the circuit(I have attached the circuit). I am feeding rectified voltage to an op-amp and I am not sure why the rectified output connected to the non-inverting terminal is held to a value (around 50mV) before it starts to follow the input voltage during the +ve half cycle. I have attached the LTSpice model and the output at the non-inverting terminal. Thanks in advance folks

 

Look at the output voltage and you will understand.
That glitch is the voltage generated by the voltage divider from the 1 megohm hysteresis resistor between the output voltage and the R1 input resistance, which gives about 20mV.

Note that only a few real world op amps will operate at a supply voltage of only 2V.

 

Look at the output voltage and you will understand.
That glitch is the voltage generated by the voltage divider from the 1 megohm hysteresis resistor between the output voltage and the R1 input resistance, which gives about 20mV.

Note that only a few real world op amps will operate at a supply voltage of only 2V.

Thanks for the reply. I changed it to 2V so that I can observe the output and the non-inverting terminal as it was not clearly visible when the supply was +15V