Your schematic shows the basics of a NAND RTL gate that I worked with in 1964 (54 years ago). In about 1966 I was working with the 74xx TTL logic family. In about 1970 and later I worked only with the CD4xxx Cmos logic family.

Is it you, your text book or your teacher that is old??

 

but notably they are all lacking in specific resistor values.

Just pick a collector resistor, pick anything since you are unsure about how much current to use and this is for testing purpose. Lets say that you pick 10k for the collector resistor, multiply that resistor 10 time to get the base resistor value: 10k x 10k = 100k

 

Your schematic shows the basics of a NAND RTL gate that I worked with in 1964 (54 years ago). In about 1966 I was working with the 74xx TTL logic family. In about 1970 and later I worked only with the CD4xxx Cmos logic family.

Is it you, your text book or your teacher that is old??

It's me that is old, I havent' been in school since the 80s.
Im near retirement and interested in a personal project to do some old-school gates that I can collect into a larger project using all transistors.
I never had any formal EE classes, just working from what I read on the web. I wanted to come up with a basic gate module that I could replicate to build larger circuits.

 

Im totally open to any "newer" design, what I really want to achieve is a modular transistor based gate that I can stack with other modules to build larger circuits.

 

At top of page select " Search Forums ". Enter " Transistor NAND Gate does not work correctly " posted by atrumblood, especially par. # 20.

 

Sorry, wsan't aware anyone was looking for a schematic.

There are a number of ways to make a gate. Knowing which you had in mind allows for more relevant answers.

I have seen a bunch of generic ones on the web, but notably they are all lacking in specific resistor values... Ill attach a picture here of what I am thinking about.

The resistor calculations are pretty straightforward.

I prefer to use NAND. With NAND, you can make any gate.

The advantage to DTL is that each input only costs you a diode.

 

It was such a long time ago that I forgot about the DTL (diode-transistor) logic family I worked with.

 

I started with TTL, then ECL. Never worked with commercial RTL or DTL.

 

interested in a personal project to do some old-school gates that I can collect into a larger project using all transistors.

There's nothing wrong with trying to do something old-school.

I saw a few digital clocks that were designed using all discrete components (other than the seven segment displays). I started designing one that would use matrix of LEDs. I designed a clocked R#S# flip flop for the counters and prototyped the logic for hours and minutes/seconds. Had too many simultaneous projects and stopped working on that in favor of more interesting projects on Raspberry Pi Zero and Arduino Uno (both were new to me a few months ago).

 

Im just in a mood to try some brute force old-school circuits, just for fun to see what I can put together. Are there better designs still using transistors than the 2 transistors in series that I showed above? I thought if I could roll some NAND transistor modules I could build more complex stuff from those modules. It would be easy to get a PCB built for such a small circuit and I could order like 10 or 20 of them for cheap. Just wanted to have a decent circuit going in so I don't waste the money on PCB's which I can't use.

 

This is the best video I have found so-far.

 

What im seeing when I try to simulate this is that the transistor is not cleanly switching from cut-off to saturation, but is going through an amplifier region. Is there a way to avoid this and go cleanly from cut-off to saturation with little to no time in the amplification region?

 

DTL NAND gate is your basic and perhaps simplest logic circuit you can create.

If you want to create your own modules, perhaps there is no need to reinvent the wheel.
Get your hands on some obsolete DEC FLIP CHIP cards such as R113 modules. They are already made for you.

If you can find a DEC 19" rack then you'll be all set to go. This one looks exactly like the one we gave away many years ago.

 

DTL NAND gate is your basic and perhaps simplest logic circuit you can create.

The question really is, what are the resistor values? When I try to use ltspice to simulate, I get wide variety of result outputs depending on the choice of the resistors. I saw the post earlier saying to choose the collector current first, then to chose the base current based on 1/100 of the collector current. If I want to light an LED, then I need approx 20ma for the collector current. 12v/0.02a=600ohm, so I tried using a 470ohm in the ltspice simulation since it was close but im not seeing clean switching from cut-off to saturation.

 

The cleanest switching action seems to happen when you use a very low base resistor. When I try 1k for the base, then I get pretty clean transitions but the collector voltage is low, only around 8v, not 12v. So, im not clear on why the base resistor affects the collector voltage when it's cut-off, shouldn't it float up to 12v since there is no path to ground?

 

Here is a NOT, AND, and OR gate (from left to right). You can make the rest once you see these:

 

What im seeing when I try to simulate this is that the transistor is not cleanly switching from cut-off to saturation, but is going through an amplifier region.

That's because you have a very slow ristime on the signal input.
Digital circuits need fast rise and fall times for the inputs to get fast switching on their outputs.
If the actual signal has a slow rise/fall time than a Schmitt trigger gate is used to speed up the transitions.

Below is the simulation with a fast input and a base current about 5% of the collector current (why did you use only 2%?).
(Also what are those odd .tran parameters you used?)
Note the clean transitions of the two outputs.
Vout1 has a slightly lower output voltage than Vout2 because of the loading from R4.

 

The question really is, what are the resistor values?

You're over thinking this.

Referring to the DTL NAND I posted earlier.

When the output is LOW, it has to be able to sink the current through R2 for any gates connected to the output. For a worst case design, you'd assume that the only one input was being driven LOW. Assuming 0V for the NAND output, the gate would have to sink the following current for every gate it was connected to.
\( \small I = \frac{V}{R} = \frac{5V-0.7V}{6.8k} = 0.63mA \)
When the NAND inputs are all HIGH, Q1 base current is:
\( \small \frac{5V-1.4V}{6.8k} = 0.48mA \)
That gives a maximum collector current of 9.6mA. I used 20 instead of 10 for beta because I'm using BC547 which is a higher beta device and the datasheet uses Ic=20Ib for saturation.

Since a LOW gate output has to sink 5mA through R1, it can sink an additional 4.6mA. Since the worst case current for driving another NAND is 0.63mA, the gate can drive 7 inputs worst case.

When I try to use ltspice to simulate, I get wide variety of result outputs depending on the choice of the resistors.

I only use LTspice when I'm not sure of my analysis or I need the results to show someone. I'm old school in that regard too.

I saw the post earlier saying to choose the collector current first, then to chose the base current based on 1/100 of the collector current.

For transistors like 2N2222 or 2N3904, 10 is usually used. For BC547, the datasheet uses 20. No one would use 100 unless it was a Darlington (I saw a number around that used in some text book for 2N3904; the author got that wrong).

If I want to light an LED, then I need approx 20ma for the collector current. 12v/0.02a=600ohm, so I tried using a 470ohm in the ltspice simulation since it was close but im not seeing clean switching from cut-off to saturation.

If you calculated 600, why didn't you use 620? That would have been the most reasonable value because with 470 (or 560), you're likely exceeding the maximum continuous forward current spec.

What do you define "clean" switching to be? Real components don't exhibit ideal behavior.

You should also note that it is inadvisable to drive LEDs with gate outputs. The standard way to do that is to use something to buffer the gate output. The last thing you want to do is design your gates so they can drive LEDs. That's going to cost you unnecessary power dissipation and increase the sink current to drive an input LOW.

 

That's because you have a very slow ristime on the signal input.
Digital circuits need fast rise and fall times for the inputs to get fast switching on their outputs.
If the actual signal has a slow rise/fall time than a Schmitt trigger gate is used to speed up the transitions.

Below is the simulation with a fast input and a base current about 5% of the collector current (why did you use only 2%?).
(Also what are those odd .tran parameters you used?)
Note the clean transitions of the two outputs.
Vout1 has a slightly lower output voltage than Vout2 because of the loading from R4.

Didn't know any other way to get an input signal (not very experienced with ltspice). The .tran was configured automatically when I run.
I don't know anything about the other tabs in the run command, so I used transient.
As for clean switching, it was my thought that the transistor would go directly from cut-off to saturation without passing through an amplification region. Is it possible to do this? If not, and I have to go through the amplification region, then I wanted it to be as small as possible to avoid undefined logic states as can be seen in the graphs I showed earlier.

 

You're over thinking this.

Referring to the DTL NAND I posted earlier.

When the output is LOW, it has to be able to sink the current through R2 for any gates connected to the output. For a worst case design, you'd assume that the only one input was being driven LOW. Assuming 0V for the NAND output, the gate would have to sink the following current for every gate it was connected to.
\( \small I = \frac{V}{R} = \frac{5V-0.7V}{6.8k} = 0.63mA \)
When the NAND inputs are all HIGH, Q1 base current is:
\( \small \frac{5V-1.4V}{6.8k} = 0.48mA \)
That gives a maximum collector current of 9.6mA. I used 20 instead of 10 for beta because I'm using BC547 which is a higher beta device and the datasheet uses Ic=20Ib for saturation.

Since a LOW gate output has to sink 5mA through R1, it can sink an additional 4.6mA. Since the worst case current for driving another NAND is 0.63mA, the gate can drive 7 inputs worst case.

I only use LTspice when I'm not sure of my analysis or I need the results to show someone. I'm old school in that regard too.
For transistors like 2N2222 or 2N3904, 10 is usually used. For BC547, the datasheet uses 20. No one would use 100 unless it was a Darlington (I saw a number around that used in some text book for 2N3904; the author got that wrong).
If you calculated 6k, why didn't you use 6.2k? That would have been the most reasonable value because with 4.7k (or 5.6k), you're likely exceeding the maximum continuous forward current spec.

What do you define "clean" switching to be? Real components don't exhibit ideal operation.

You should also note that it is inadvisable to drive LEDs with gate outputs. The standard way to do that is to use something to buffer the gate output. The last thing you want to do is design your gates so they can drive LEDs. That's going to cost you unnecessary power dissipation and increase the sink current to drive an input LOW.

Im just not clear on the diode configuration for the DTL, at least it's not like anything I have been reading about so-far, which all seem to be base resistors feeding a network of transistors to a collector transistor output. The DTL configuration you show is just not what I had in my head from other reading, so it doesn't really look like what I was expecting, so im less familiar with it than the straight transistor configuration. Not that I have any real familiarity with either...