first fpga schematic and pcb design help

Thread Starter


Joined Apr 3, 2019
hello! i am a second year first semester EENG student, and for the digital project this semester we are tasked with programming a fpga to do something (i.e. clock, calculator, stop light, etc).

*the project requirements does not include creating a circuit. most/all are simply using the on-board IO on the basys3 development board.
*i am not asking for code, only schematic/ pcb help.

for my project i want to create something like this:

below is my schematic, but first i will describe it to the best of my ability. i want for the motor (12vdc) to spin at a speed set either by the on-board potentiometer or via SPI, whenever a switch is triggered (if you watch the video, the switch is on the arm), for a set amount of time. this will control a total of three spool holders (systems of 1x POT, 1x Switch, 1x Motor, 2x LED). led EN shows whether or not the POT is enabled or is under SPI control, and led TR shows whether the motor is triggered (active).

all parts excluding headers are SMD, and resistors/ capacitors are all package size 0805 (excluding the four electrolytic). the FPGA is a LCMX02. it uses two mx1508 motor drivers, which can control a total of four motors, but in this application only three are being used. for the 3.3v supply i am using a LM2596SX-3.3, using the provided schematic in the datasheet. because the spi control signal will be provided by an "arduino", i need a bi-directional logic shifter, and for this im using a TXS0108e. DATASHEET: in the datasheet it says that when the OE input is high, data can be passed through. in my design am i doing this correctly?

another question i have is the power filtering/ decoupling section of the schematic. having no experience with this i used an example i found online. is this correct? do i need to use ferrite bead or the capacitors (x3) beforehand, or is the power from the regulator good enoughph? if i need the ferrite bead, what value should i use?

another question i have is about my inputs/ outputs. there are 6 leds (0805 smd), 3 potentiometer, and three switches. are the potentiometers/ other IO wired correctly?

my final question pertains to the motor drivers. in the schematic, the unused inputs/ grounds/ power are disconnected. do i need to do anything with these, or simply leaving them disconnected fine?

if anyone has any input on my design, or see any problems, please let me know. thanks! after i finish the schematic, i will start laying out the PCB.

EDIT: upon further thought, i probably need an ADC for the potentiometers. suggestions?
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Thread Starter


Joined Apr 3, 2019

did i post this in the wrong section? if so, how do i move it?

a bit of an update on this project. so i have finalized the PCB/ schematic (shown below), but my same questions still remain.

the passives are mostly 0805 and 0603

the top layer is +3.3v, and the bottom is gnd.

Attached are pictures of the back and front of the pcb in both photo and design modes, and my schematic.


-is 6mil big enough for traces? (see pics) obviously not all traces are 6mil, but most are.
-does the schematic look good (design wise)? i've never done a fpga design before, so i dont know. in designs i've seen they have used ferrite beads to aid in power filtering. do i need one? i've got some for the ADC already
-is the component placement on the PCB good?

here are some pictures:

if anyone has any input on my design, sees any problems, or can share personal experience it would be greatly appreciated!




Joined Mar 8, 2009
A quick review...

- Wire up power and ground to the second half of U5, and tie InA2 and InB2 to put the driver in an idle state, Inputs and power rails should never be left floating
- There is a 4-way (+) junction to the bottom of C12. It is better to draw it as two 3-way junctions. I avoid all 4-way junctions to avoid the "do these wires cross or are they connected" questions or glitches
- U3: Conventionally, schematics are drawn flowing left to right. Also, I would move D2 to be vertical between the U3/L2 junction and ground so the design is clearer. See how the schematic is drawn in the data sheet for U3
- U4/U5 should have a 100n cap from +3_3V to GND each. Rule of thumb is to bypass every power pin and place the cap as close to the pin as possible.

- 6 mil is fine for logic traces. Power traces should be much larger to reduce voltage drop and trace impedance.
- The top pour has many floating unconnected islands of copper. These can act as antennas and cause unwanted EMI emissions
- Bypass cap grounds should have as short as possible trace to a via to the ground pour.
- Look at the data sheet for how to route the switching regulator. Long thin traces and chopped ground pours are asking for trouble with stability and EMI
- There are no mounting holes. Also, add in silk the board name and revision


Thread Starter


Joined Apr 3, 2019


so i normally do put vias as close to the grounds of components as possible. i used a auto-router for all of the logic traces, but forgot to exclude the power/ground nets, and didn't notice. (i hand route all the higher power traces)

so i shouldn't keep the "islands" on the pours. got it, makes alot of sense now that i think about it. how big of an issue is this though? I've done projects in the past using 8-bit controllers (atmel atmega series), and have kept them in and haven't noticed anything wrong.

should i just tie InA2 and InB2 to ground to put them into idle? i also added those capacitors.

ok i added those capacitors.

so on the pcb design the top pour (+3.3v) has a long way to travel in some areas to get to the fpga pins. is this ok?

i added the mounting holes and board name. i do this as my "last step", as i like to have my component placement and routing done first.

here is an updated schematic:

thanks for your help! it is greatly helped me on this project.

EDIT: Added a better schematic. this is the "final" version, unless me or someone else sees something wrong/improvable.

EDIT #2: Added a Multiplexer, so updated pcb and schematic pictures. is this implemented correctly?


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