I understand what you are saying - but the problem with having the capacitor on the low voltage side, especially for a high voltage supply of -6kV like mine, the desired ripple of 0.1V is also divided down by the resistive divider circuit, which has a voltage ratio of 2000 in my case. A 3V reference voltage for a -6kV output. So that 0.1V is basically within the range of noise when divided down by that much. So the only way to extract the actual voltage ripple from the circuit is to have the isolation capacitor on the high voltage side - but for some reason, in my simulation, you may see that it does let some DC through the isolation capacitor, which doesn't make sense because of how capacitors are supposed to work!

OK, and indeed the ripple would also be divided, So how about a capacitive divider? Or maybe NOT!
The unfortunate reality is that real capacitors do have some leakage, and that will cause problems. one option might be to provide a low impedance drain that would be a resonant circuit at the ripple frequency. But that would distort the ripple into a sine wave, so that may not work adequately.
How long do you need to examine the ripple waveform? A small battery powered transmitter floating at the output voltage could provide excellent isolation, and avoid any DC offset issues.

 

hi SiC,
Check this circuit section, made a change to the level shift.
E
Added more detail:

 

I do detect some waveform distortion, if the input is a sine wave. Adjust R14 to provide no distortion with the anticipated input signal. Presently there is total clipping between Va and Vd, and so unless you are only interested in frequency there is no other useful information available by that point.

 

H B,
There is no distortion, no clipping, the input is not a Sine wave the input waveform has been intentionally formed in that way in order to do the tests I wanted to try in simulation that would help the TS.
If you had taken the trouble to read the test signal setup parameters, this would be obvious.

There is useful information in the result, if you know what to look for.
E

 

Hi SiC,
These two sims show the OPA section.
When the ‘ripple’ signal Va has an initial offset of 25Vdc, which would happen in the real hardware, the settling time is about 10mSec.
This is due to C5, 10n charging via R9 100K and this is typical.

After 10mSec the OPA section is stable.

The second sim shows the operation with a 1MHz, 60mV Sine wave, the response looks OK, it is just exceeding the VH and VH levels. [ No 25Vdc offset, for Test only]

E

 

Hello,

I have designed a high voltage output (6000V) supply using a fly-back converter. I need to measure the output voltage with a DSP, but the output voltage must be at most 0.1V. This is not achievable with the 12-bit or 16-bit single ended/differential sensors on the TI DSP board that I am using to control it. I instead want to extract, measure, and amplify the output voltage ripple and use that within the control system. The method I have used is the most simple, but it doesn't seem to be performing as I desire. I will attach an .asc simulation of the circuit. It seems that the DC offset is not being added to the AC ripple - I am using a 3V supply and two 10K resistors to offset by 1.5V, which is the mid-range of the ADC input of 0-3V.

Is there a better way to do this, or any suggestions to improve this existing circuit? Can anyone help me understand what is going wrong? This is the most simple method I know of adding DC offset.

SiC

I would have thought that the simplest way would be to modify the potential divider that connects the DC to your a/d so that it has a different division ratio for AC than it does for DC.
This would divide by 2000 at DC, but only divide by 20 at frequencies >1kHz. Then you could read a single A/D and get both answers simultaneously.
It is easy to extract the rms ripple voltage as is simply the square root of the variance (the standard deviation), and the variance is easy to extract from a sampled waveform.

 

The original sin is the transient analysis over 20 milliseconds for a 500kHz signal.
I laways choose a duration that shows 5-10 cycles only. The total duration being long enough to let the circuit settle.
So the command I chose is .tran 0 2m 1.98m
The issues are immediately apparent then.

 

The original sin is the transient analysis over 20 milliseconds for a 500kHz signal.
I laways choose a duration that shows 5-10 cycles only. The total duration being long enough to let the circuit settle.

hi jlm,

The first image shows the expanded time scale.

That second image, simulation time was chosen to show the TS the charge time of the input capacitor, before the circuit stabilized.

E

 

H B,
There is no distortion, no clipping, the input is not a Sine wave the input waveform has been intentionally formed in that way in order to do the tests I wanted to try in simulation that would help the TS.
If you had taken the trouble to read the test signal setup parameters, this would be obvious.

There is useful information in the result, if you know what to look for.
E

I do not have that simulation software and so reading that ".asc file is not possible for me.

 

I do not have that simulation software and so reading that ".asc file is not possible for me.

Hi B,
With due respect, you should not attempt to analyse and post misleading information describing circuitry you do not understand.

If you have a doubt or query about any post, just ask.

E

 

Given that no mention was made about the wave form, and given that the original discussion is about analyzing the ripple, and given that while the two wave form displays did have the voltage spans that the T requested, it was reasonable to presume that either the input was excessive or that the gain was leading to saturation and clipping. It had not occurred to me that other than a sine wave would be used, as there was no reason to use anything else.

 

I would have thought that the simplest way would be to modify the potential divider that connects the DC to your a/d so that it has a different division ratio for AC than it does for DC.View attachment 257262
This would divide by 2000 at DC, but only divide by 20 at frequencies >1kHz. Then you could read a single A/D and get both answers simultaneously.
It is easy to extract the rms ripple voltage as is simply the square root of the variance (the standard deviation), and the variance is easy to extract from a sampled waveform.

The only challenge that I see with this circuit is obtaining a 6000 volt capacitor. Yes, a compensated attenuator would provide the desired results.

 

The only challenge that I see with this circuit is obtaining a 6000 volt capacito

hi B,
Large selection available.
E
https://www.rhopointcomponents.com/...e-high-voltage-np0-capacitor-series-2kv-10kv/


https://www.google.com/search?q=47n...UKY8AKHcSSA90Q_AUoAXoECAEQAw&biw=1411&bih=864

 

The only challenge that I see with this circuit is obtaining a 6000 volt capacitor. Yes, a compensated attenuator would provide the desired results.

I thought of that, but they seem more common that I expected
https://uk.rs-online.com/web/p/single-layer-ceramic-capacitors/8313272
The attenuator could easily be rearranged to put several capacitors in series.

 

I thought of that, but they seem more common that I expected
https://uk.rs-online.com/web/p/single-layer-ceramic-capacitors/8313272
The attenuator could easily be rearranged to put several capacitors in series.
View attachment 257279

OK, yes, they are made and available, but not as available as the lower voltage ones. I did not intend to imply unavailable, only that many electronic parts places may not stock them.

 

The only challenge that I see with this circuit is obtaining a 6000 volt capacitor.

Hi B,
A quick check shows there are a number of sources for these capacitors, there is nothing unusual in this type of HV capacitor, they are common in HV flyback circuits.

Even Ali-Express and Ali BaBa stock them.
E

 

Hello

I know this is your earlier version but I think it will work.
I've substituted a voltage source for the boots converter to speed up sim interations and kept the boost components I thought would affect test of the remaining circuit. It basically simulates the Boost output waveform after settling. This is mainly for proof of concept.
Anyway, I think most of the changes are self explainatory. The AD8041 opamp disable pin is active low, and they were all connected to ground (I reconnected each to +V). You could probably do this with single supply opamps and bias at half of 3V supply. I showed an 74HC132 for the NAND gate. Looks like the gate needs to wait for the boost signal to settle.

 

Hello

I know this is your earlier version but I think it will work.
I've substituted a voltage source for the boots converter to speed up sim interations and kept the boost components I thought would affect test of the remaining circuit. It basically simulates the Boost output waveform after settling. This is mainly for proof of concept.
Anyway, I think most of the changes are self explainatory. The AD8041 opamp disable pin is active low, and they were all connected to ground (I reconnected each to +V). You could probably do this with single supply opamps and bias at half of 3V supply. I showed an 74HC132 for the NAND gate. Looks like the gate needs to wait for the boost signal to settle.

View attachment 257296

View attachment 257297

View attachment 257298

Hello EE,

I am still working on this little idea. Could you send me this .asc file so I can take a look. For some reason the schematic will not load correctly on my computer.

I have took a slightly different route now that seems to work quite nicely, which uses a band-pass filter to isolate the ripple at the switching frequency. Means that the attenuation at 0Hz is much better and filter settling time doesn't have much of an impact. I am just trying now to get the correct logical signals to trigger the PWM output to keep the output voltage nicely between the set limits. I'll attach a new schematic just so anyone who is following can keep track of the progress.

The function I am trying to achieve is to turn the fly-back switch OFF when the ripple that is amplified exceeds the upper limit, and leave the switch OFF until the ripple voltage falls below the lower limit. The hard part is avoiding having the switch turn ON once it falls back within the window but has not fallen below the lower reference voltage. If I cannot avoid that, the converter would just act like a hysteretic comparator that tracks the upper reference voltage and the comparators may behave erratically. I want just one "inhibit" or "enable" signal per switching period. Maybe a flip-flop of sorts is required, but I've had no luck with that either. I have attached a waveform which might help demonstrate the point. I understand I have deviated a fair bit from the original point of the post but any help would be appreciated.


Best,
SiC

 

The function I am trying to achieve is to turn the fly-back switch OFF when the ripple that is amplified exceeds the upper limit, and leave the switch OFF until the ripple voltage falls below the lower limit. The hard part is avoiding having the switch turn ON once it falls back within the window but has not fallen below the lower reference voltage. If I cannot avoid that, the converter would just act like a hysteretic comparator that tracks the upper reference voltage and the comparators may behave erratically. I want just one "inhibit" or "enable" signal per switching period. Maybe a flip-flop of sorts is required, but I've had no luck with that either. I have attached a waveform which might help demonstrate the point. I understand I have deviated a fair bit from the original point of the post but any help would be appreciated.

This circuit below should work. However, keep in mind this is proof of concept only.
U3A and U3B are single supply voltage comparators with outputs normally HIGH. When the MIN ripple value is exceeded at the input of U3B the output state changes to Low. Likewise, for U3A, when the MAX ripple value is exceeded, its output goes Low.
U4A-U4C form an "OR" gate. The flipflop "set" input inhibits the SMPS when Q output goes high, and the "clr" input permits the SMPS oscillator to run when Q goes low. I envision the INH line to drive a NMOS mosfet that will either shunt, or not, the SMPS oscillator timing capacitor (since it doesn't have an "enable pin").

Anyway, at startup both comparator outputs go high, enabling the SMPS to startup. The BUF_out signal is driven by an RMS-to-DC converter that outputs a DC level value that is equal to the ripple RMS value. As the ripple value rises it exceeds the MIN value, and may, or may not, exceed the MAX value. If it doesn't exceed the MAX value, the FF retains is initial state (reset). If it does, the FF changes to its "set" state and inhibits the SMPS. When the output falls below the MAX level, the FF retains its "set" state until the RMS value falls below the MIN value. The FF then becomes "reset" and the SMPS oscillator begins running again. I didn't show it but the comparators should have hysteresis applied.

You should use an SMPS chip that has an enable pin and also think about using single supply devices.

 

This circuit below should work. However, keep in mind this is proof of concept only.
U3A and U3B are single supply voltage comparators with outputs normally HIGH. When the MIN ripple value is exceeded at the input of U3B the output state changes to Low. Likewise, for U3A, when the MAX ripple value is exceeded, its output goes Low.
U4A-U4C form an "OR" gate. The flipflop "set" input inhibits the SMPS when Q output goes high, and the "clr" input permits the SMPS oscillator to run when Q goes low. I envision the INH line to drive a NMOS mosfet that will either shunt, or not, the SMPS oscillator timing capacitor (since it doesn't have an "enable pin").

Anyway, at startup both comparator outputs go high, enabling the SMPS to startup. The BUF_out signal is driven by an RMS-to-DC converter that outputs a DC level value that is equal to the ripple RMS value. As the ripple value rises it exceeds the MIN value, and may, or may not, exceed the MAX value. If it doesn't exceed the MAX value, the FF retains is initial state (reset). If it does, the FF changes to its "set" state and inhibits the SMPS. When the output falls below the MAX level, the FF retains its "set" state until the RMS value falls below the MIN value. The FF then becomes "reset" and the SMPS oscillator begins running again. I didn't show it but the comparators should have hysteresis applied.

You should use an SMPS chip that has an enable pin and also think about using single supply devices.

View attachment 257505

Hello EE,

Thank you for the above message. First of all could I ask, why do you suggest single supply devices rather than rail to rail dual supply devices? Could you describe the benefits when working with AC signals that can swing positive and negative? How do you ensure that the negative part of an AC signal is preserved?

I assume BUF_OUT is where the voltage ripple is after extraction and amplification. My question then is why are the limits 300mV and 150mV - these seem quite low. I think maybe I am missing part of the schematic which would explain what is happening. Would you mind sending the .asc file so that I can simulate it on my SMPS?

I actually managed to get something similar working today on my computer. Instead of a JK Flip flop (I couldn’t find one on my LTSpice - you must be using a custom model?) I used an SR flip flop with an ENABLE input. The S and R inputs are from the comparators which tell me whether the minimum ripple or the maximum ripple has been exceeded. Buy only allowing the state of the SR flip to enable a change of state when the window comparator gives an output of 0, the output of the flip flop latches ON until the max voltage ripple is exceeded and latches OFF until the minimum is exceeded. You are right in that I need to use hysteresis for my comparators. When I am back at my labs tomorrow I will attach the .asc file that I created today to compare the solutions.
Thanks again for your help, it is appreciated.
SiC