Hello EE,

Thank you for the above message. First of all could I ask, why do you suggest single supply devices rather than rail to rail dual supply devices? Could you describe the benefits when working with AC signals that can swing positive and negative? How do you ensure that the negative part of an AC signal is preserved?

If you bias the opamps at 1/2 vcc, then the AC signal will be centered at 1.5v for VCC=3V (just like you did for the buffer to your ADC) and you won't need dual supplies. If centered at 1.5v, the signal can still swing negative up to 1.5v (for 3v supply). Whether or not this will work for your design depends on the required voltage swing. But RR opamps that can swing close to VCC/gnd (for single supply opamp) would be best. Since I converted the ripple value to a DC value (using and RMS-to-DC converter), I didn't have to do this.

I assume BUF_OUT is where the voltage ripple is after extraction and amplification. My question then is why are the limits 300mV and 150mV - these seem quite low. I think maybe I am missing part of the schematic which would explain what is happening. Would you mind sending the .asc file so that I can simulate it on my SMPS?

BUF_Out on my diagram is the output of an RMS-to-DC converter chip (AD536), a chip that's been around for a long time. It's input is AC coupled thru a cap to the output of the SMPS. Its job is to read the AC ripple signal and convert it to an RMS DC voltage equivalent value. I've attached a datasheet if you want more info.

The ripple limits are arbitrary, you'll need to determine those yourself.

I actually managed to get something similar working today on my computer. Instead of a JK Flip flop (I couldn’t find one on my LTSpice - you must be using a custom model?) I used an SR flip flop with an ENABLE input. The S and R inputs are from the comparators which tell me whether the minimum ripple or the maximum ripple has been exceeded. Buy only allowing the state of the SR flip to enable a change of state when the window comparator gives an output of 0, the output of the flip flop latches ON until the max voltage ripple is exceeded and latches OFF until the minimum is exceeded. You are right in that I need to use hysteresis for my comparators. When I am back at my labs tomorrow I will attach the .asc file that I created today to compare the solutions.
Thanks again for your help, it is appreciated.
SiC

Sounds like your using the LTspice native digital "A" devices, which is ok, but you have to use them correctly or they will fool you. They are not models of any particular vendors components. You have to take the time to set all the necessary parameters. The components I use are from digital libraries modeled after specific family of devices.
Somewhere on this site there is a link to "Bordodynov" spice library that is pretty extensive. You might want to download it.

 

A SET / RESET flip-flop is the function required, and so a CD4013 will work very well, however, I got the logic levels backward. The 4013 is hi=true.
If the ripple is generated by the flyback supply operation then it should vanish when the supply switches off. Is there another source of ripple?? Based on these last posts the project has become confusing to me.
AND, really, the function described of switching on at a higher level and then not switching back until a lower level is reached is simple to do with a single comparator. Positive feedback is used, (output to non-inverting input) and that reduces the trigger level needed from the signal source to some lower value. One resistor is all that it takes. It also serves to speed the transition of the comparator when the input is changing slowly.

 

A SET / RESET flip-flop is the function required, and so a CD4013 will work very well, however, I got the logic levels backward. The 4013 is hi=true.

The 4000 family might be too slow for this application. hence, the 74HC family.

If the ripple is generated by the flyback supply operation then it should vanish when the supply switches off. Is there another source of ripple?? Based on these last posts the project has become confusing to me.

The ripple diminishes along with the output voltage when the SMPS stop operating.

AND, really, the function described of switching on at a higher level and then not switching back until a lower level is reached is simple to do with a single comparator. Positive feedback is used, (output to non-inverting input) and that reduces the trigger level needed from the signal source to some lower value. One resistor is all that it takes. It also serves to speed the transition of the comparator when the input is changing slowly.

A diagram of your suggestion is welcome.

The TS was using a few opamps to do filtering and extraction for this circuit, I used my own approach and used an RMS-to-DC converter to do the extraction and conversion to a proportional DC voltage. My last post described the comparator stages only. May that is what confused you...

 

The 4000 family might be too slow for this application. hence, the 74HC family.



The ripple diminishes along with the output voltage when the SMPS stop operating.



A diagram of your suggestion is welcome.

The TS was using a few opamps to do filtering and extraction for this circuit, I used my own approach and used an RMS-to-DC converter to do the extraction and conversion to a proportional DC voltage. My last post described the comparator stages only. May that is what confused you...

I am not able to provide a diagram. What I suggest is simply adding a bit of hysteresis to the comparator by adding a bit of POSITIVE feedback. That works with comparators, which I understand very well. I see the comparators and I am quite familiar with the difference, and that is why some positive feedback through a high value resistor, possibly one megohm, is in order.
What the positive feedback does is to separate the switch on voltage point from the switch off voltage point. Usually that is done to avoid oscillation when the rate of change of the input is much slower than the response time of the comparator.

 

A SET / RESET flip-flop is the function required, and so a CD4013 will work very well, however, I got the logic levels backward. The 4013 is hi=true.
If the ripple is generated by the flyback supply operation then it should vanish when the supply switches off. Is there another source of ripple?? Based on these last posts the project has become confusing to me.
AND, really, the function described of switching on at a higher level and then not switching back until a lower level is reached is simple to do with a single comparator. Positive feedback is used, (output to non-inverting input) and that reduces the trigger level needed from the signal source to some lower value. One resistor is all that it takes. It also serves to speed the transition of the comparator when the input is changing slowly.

I understand the confusion. Actually, my power supply must have a fixed frequency, so I do not plan to completely turn off all switching, but output the minimum allowed duty cycle, and when the lower voltage level is triggered, output the PWM from the controller chip. The reason I need these circuits is to increase the accuracy at which the output voltage can be regulated. It is my vision that by regulating the ripple in this way, the average DC output voltage will be much closer to the set output voltage than would otherwise be obtained with a 12-bit ADC chip. This is the main reason for the circuit. By outputting a minimum duty cycle there will always be a ripple at the switching frequency, which hopefully the op-amps are able to track efficiently.
A single comparator, I think, will not do. I need to check when the ripple is high and when it is low, and then the SR flip-flop ensures that its output state only changes when these signals are applied. I have attached a diagram of what I have achieved thus far. I may attempt to replicate the RMS-to-DC converter solution, because there are probably a lot more interesting things I could do in my DSP with a DC input voltage, but I am still slightly unsure about how the circuit by EE works. Need to spend a bit more time crunching it!

Hopefully a bit more sense has been made of the problem/solution?

SiC

 

If you bias the opamps at 1/2 vcc, then the AC signal will be centered at 1.5v for VCC=3V (just like you did for the buffer to your ADC) and you won't need dual supplies. If centered at 1.5v, the signal can still swing negative up to 1.5v (for 3v supply). Whether or not this will work for your design depends on the required voltage swing. But RR opamps that can swing close to VCC/gnd (for single supply opamp) would be best. Since I converted the ripple value to a DC value (using and RMS-to-DC converter), I didn't have to do this.



BUF_Out on my diagram is the output of an RMS-to-DC converter chip (AD536), a chip that's been around for a long time. It's input is AC coupled thru a cap to the output of the SMPS. Its job is to read the AC ripple signal and convert it to an RMS DC voltage equivalent value. I've attached a datasheet if you want more info.

The ripple limits are arbitrary, you'll need to determine those yourself.



Sounds like your using the LTspice native digital "A" devices, which is ok, but you have to use them correctly or they will fool you. They are not models of any particular vendors components. You have to take the time to set all the necessary parameters. The components I use are from digital libraries modeled after specific family of devices.
Somewhere on this site there is a link to "Bordodynov" spice library that is pretty extensive. You might want to download it.

Interesting solution, however I think the band-width of the solution is too low. I plan to operate the fly-back in hundred of kilohertz range, and possibly even 1MHz or so. That's why I am using these op-amps which have 500Mhz GBW - but even they are suffering distortion. The 4GHz model in LTSpice is replicating the ripple well, but has 100MHz oscillations at the output, which is obviously cause for concern.

SiC

 

To remove the ripple, especially since it is a fairly high frequency, you can add a stage of filtering. If the current is fairly low then a series choke will not be very heavy, although it will need to be adequately insulated if it is mounted and not supported by it's leads.
How closely regulated does the high voltage need to be? And does it need to be electronicly varied? If varied, how fast? How fast does the regulator have to respond to load changes? And how big are any load changes? These are questions relevant to any regulated power supply.

It does not take a whole lot of capacitance to smooth out any ripple at 100KHz. It make a lot more sense to filter the voltage than to struggle with trying to regulate-out the ripple.. Almost all power supplies use at least two sections of filtering, and that is just for average applications.
If this is the same power supply as I saw in an earlier thread a while back, the filtering was not very much. Adequate filtering is often much simpler than regulating the ripple out.

And once again, a fast comparator with no hysteresis is going to oscillate, unless both inputs come from ZERO impedance sources. Not low impedance, but ZERO. So to avoid that problem, add a small bit of positive feedback. If you doubt this claim of mine, just check the applications notes for most fast comparators.

 

To remove the ripple, especially since it is a fairly high frequency, you can add a stage of filtering. If the current is fairly low then a series choke will not be very heavy, although it will need to be adequately insulated if it is mounted and not supported by it's leads.
How closely regulated does the high voltage need to be? And does it need to be electronicly varied? If varied, how fast? How fast does the regulator have to respond to load changes? And how big are any load changes? These are questions relevant to any regulated power supply.

It does not take a whole lot of capacitance to smooth out any ripple at 100KHz. It make a lot more sense to filter the voltage than to struggle with trying to regulate-out the ripple.. Almost all power supplies use at least two sections of filtering, and that is just for average applications.

And once again, a fast comparator with no hysteresis is going to oscillate, unless both inputs come from ZERO impedance sources. Not low impedance, but ZERO. So to avoid that problem, add a small bit of positive feedback. If you doubt this claim of mine, just check the applications notes for most fast comparators.

I do not doubt the solution of the positive feedback whatsoever, sorry if I gave that impression! I will certainly add those when I create the final prototype!

Regarding the SMPS, here is my task:
6000V output, 100mV ripple. The problem is not filtering, the problem is that with digital controllers, the 12-bit ADC's on board do not have sufficient resolution to keep the output voltage within this specification at steady-state. During transients, the output voltage can swing +/-5V, which could be achieved the standard ADC's, but the problem is at steady-state. However, the output pulses can be anywhere from 100Hz to 100kHz and are from full load to absolute zero load. In reality I would have zero understanding of which pulse regime is present at the output, but for my prototype I will control a high voltage switch which emulates the load pulsing. I have designed an output filter that is a three stage LC low-pass filter, which should achieve the output ripple of 0.1V - but this does not mean I can necessarily regulate it to that level without the use of classical analogue electronics. An external ADC with much more resolution is a solution, but unfortunately this introduces way too much latency between the load voltage changing and the time taken to calculate and send to the DSP a very high resolution result.

Thus, I decided that the only way to achieve this and possibly control the output with a much faster response is to use the above solution, this way the resolution of the ADC is not a problem. Standard feedback control will be used for the majority of the time, but this "blanking" of the PWM will stop the PWM from switching if the standard 12-bit ADC outputs a duty cycle that is too high and exceeds the required level. So just to reiterate, I have no issue achieving the ripple level, just measuring it and regulating the output to the required accuracy to meet the specification. Of course, a standard analogue controller would do the trick, but my project requires investigating controlling a travelling wave tube type device with digital controllers.

Do let me know if more questions arise.

SiC

 

OK, the requirement is very tight regulation, less than 0.1% deviation at 6000volts. And pulsed loads jumping up and down in some unknown random manner. The obvious solution ( A very high current capability to effect a very low effective supply internal resistance) is not possible and so very fast regulation is the only choice. That seems like the realm of a fast analog regulator with digital assistance. Neither simple nor easy.

 

OK, the requirement is very tight regulation, less than 0.1% deviation at 6000volts. And pulsed loads jumping up and down in some unknown random manner. The obvious solution ( A very high current capability to effect a very low effective supply internal resistance) is not possible and so very fast regulation is the only choice. That seems like the realm of a fast analog regulator with digital assistance. Neither simple nor easy.

Pretty much, yes. I have already programmed a digital controller for the solution. I suppose my choice is the opposite of what you stated here - a digital controller for the majority that instead has some analogue assistance when within a certain range of regulation. I also envisage the solution will help me during transients. The fly-back has the issue of a RHP Zero which typically causes issues with the response at transients anyway due to limited cross-over frequency. The DSP I have has what is called a Configurable logic block, similar to an FPGA. I am not sure yet how to use it, but it may help me reduce the number of analogue components needed external to the DSP. I cannot think of any other way to achieve what I need than this solution.

SiC

 

I am not able to provide a diagram. What I suggest is simply adding a bit of hysteresis to the comparator by adding a bit of POSITIVE feedback. That works with comparators, which I understand very well. I see the comparators and I am quite familiar with the difference, and that is why some positive feedback through a high value resistor, possibly one megohm, is in order.
What the positive feedback does is to separate the switch on voltage point from the switch off voltage point. Usually that is done to avoid oscillation when the rate of change of the input is much slower than the response time of the comparator.

Yes...the needed hysteresis was mentioned back in post #39 and #40.

 

Interesting solution, however I think the band-width of the solution is too low. I plan to operate the fly-back in hundred of kilohertz range, and possibly even 1MHz or so. That's why I am using these op-amps which have 500Mhz GBW - but even they are suffering distortion. The 4GHz model in LTSpice is replicating the ripple well, but has 100MHz oscillations at the output, which is obviously cause for concern.

SiC

Yes...I was concerned about the bandwidth for that model but forgot to mention it. There are faster converters available.

 

Yes...I was concerned about the bandwidth for that model but forgot to mention it. There are faster converters available.

The highest I have found is 8MHz (AD637J) which I think would still not perform the function correctly. Do you happen to have on hand the model number for one you may have used for higher frequency signals? Am I right in thinking that this is just another way to achieve the function I described or did you envisage the RMS to DC converter could be used in a different way? I think if you could share the .asc file I could understand slightly better the functionality of the chip? I'll see about getting those comparators models into my LTSpice for future use. Thanks for that.

Best,
SiC

 

If the 12bit A/D converters do not have enough resolution when covering 0-6000+ volts, you might be able to use a scheme of shifting the range using an offset scheme, if all the voltage that you need to see is around 6000 vvolts.Boosting the bottom end you could have the range as 5600 volts at the low end and 6100 volts at the high end. Analog off setting is not that difficult. You will need t add digital isolation, though.

 

If the 12bit A/D converters do not have enough resolution when covering 0-6000+ volts, you might be able to use a scheme of shifting the range using an offset scheme, if all the voltage that you need to see is around 6000 vvolts.Boosting the bottom end you could have the range as 5600 volts at the low end and 6100 volts at the high end. Analog off setting is not that difficult. You will need t add digital isolation, though.

Can you expand on this point or provide me with a reference document that explains it in greater detail? I'm quite puzzled by it, but then again I've never heard of this technique before. With 12-bits, the number of usable levels is 4096. Even with the range you stated (500V), each level in the ADC corresponds to 122mV/level, and that's before even considering other errors that can be seen with an ADC such as offset/linearity errors. I think that using such techniques for ultra low noise supplies just doesn't cut it.

SIC

 

Regarding the SMPS, here is my task:
6000V output, 100mV ripple.

Am I reading this correctly? Six thousand volts? with 100mV ripple?

 

Am I reading this correctly? Six thousand volts? with 100mV ripple?

Correct. This is actually way too high for the application - the company I work for achieve micro volt levels of ripple on higher voltage outputs. Fortunately I am tasked as a PhD student to develop a new topology and control system so they are less stringent with me.
Best,
SiC

 

OK, the offset scheme would, in my quick example, have 5600 volts appear as a binary zero, and the 6100 volts, as an example, appear as full scale. that may not yet be adequate resolution, at 4096 counts/500 volts, not quite ten counts per volt. I picked too wide a span.
What the offset does is replaces the "zero volts" reference point with a "perfectly constant" higher voltage. The result being that the quantity being measured is now the difference between two points that are not ground. So not nearly as much attenuation needed, and less chance for noise to be a problem. The down side is that the A/D converter package is far off ground and must be isolated. With serial communications that is not too many isolation lines, if it is fast enough. That part we do not know.
Hopefully this explanation makes some sense.

 

OK, the offset scheme would, in my quick example, have 5600 volts appear as a binary zero, and the 6100 volts, as an example, appear as full scale. that may not yet be adequate resolution, at 4096 counts/500 volts, not quite ten counts per volt. I picked too wide a span.
What the offset does is replaces the "zero volts" reference point with a "perfectly constant" higher voltage. The result being that the quantity being measured is now the difference between two points that are not ground. So not nearly as much attenuation needed, and less chance for noise to be a problem. The down side is that the A/D converter package is far off ground and must be isolated. With serial communications that is not too many isolation lines, if it is fast enough. That part we do not know.
Hopefully this explanation makes some sense.

Yes. Makes perfect sense, and is definitely a possible solution. Would need to be an external ADC as the ones on the DSP can’t be changed, so as you say would depend on how fast the communications between the Master and slave would be with SPI for example. Plenty for me to get on with anyway. Thanks again for all your help.