Dual Pulse Generator Circuit Explanation

Can someone help me fully understand this circuit? Specifically what happens when both NMOS of TG1 and TG2 are on.

 

But TG1 and TG2 are never both ON. So why do you think that they are both ON ?

 

When CLK changes from 0-1 the output of inverter I2 changes from 0-1 after some delay turning ON the NMOS of TG1 and turning off the PMOS of TG2. The NMOS of TG2 is still on for another inverter delay. My confusion is what happens at that time.