Dual Pulse Generator Circuit Explanation

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Discussion in 'Homework Help' started by josb10, Apr 16, 2016.

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  1. Apr 16, 2016 #1
    josb10

    Thread Starter New Member

    Mar 20, 2013
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    upload_2016-4-16_19-55-41.png
    Can someone help me fully understand this circuit? Specifically what happens when both NMOS of TG1 and TG2 are on.
     
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  2. Apr 17, 2016 #2
    Jony130

    AAC Fanatic!

    Feb 17, 2009
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    But TG1 and TG2 are never both ON. So why do you think that they are both ON ?
     
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  3. Apr 17, 2016 #3
    josb10

    Thread Starter New Member

    Mar 20, 2013
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    When CLK changes from 0-1 the output of inverter I2 changes from 0-1 after some delay turning ON the NMOS of TG1 and turning off the PMOS of TG2. The NMOS of TG2 is still on for another inverter delay. My confusion is what happens at that time.
     
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