First pass at a schematic as described in #18.

R1-C1 are the monostable timing components. Their values are approximate because the input transition voltage levels in the 4093 are not tightly controlled in fabrication.

When both Y5 output are high (even for a few nanoseconds), U1A goes low and triggers the monostable. While it is timing, feedback from pin 10 to pin 11 prevents extra input activity from re-triggering the timer. The output is inverted in U1B to get the correct logic polarity for Q1.

A potential problem is that the 4017 outputs sometimes have very short glitches caused by the way the outputs are decoded from a shift register. To prevent these from creating false triggers, add a small R-C filter at U1A pins 1 and 2. 0.1 uF and 1.0 K should work.

ak

 

R1-C1 are the monostable timing components. Their values are approximate because the input transition voltage levels in the 4093 are not tightly controlled in fabrication.

How you control the timing here to be 3 seconds as the post owner need?
Charging and sicherging capacitor?, the c1? , for a certain value of capacitor?
I think the circuit in post #20 is more simple and clear using 555 ic

 

C1 and R1 control the time.... 10uF * 300k = 3sec.
if needed to adjust it, use small R1 value in series with potentiometer

 

How you control the timing here to be 3 seconds as the post owner need?
Charging and sicherging capacitor?, the c1? , for a certain value of capacitor?

https://en.wikipedia.org/wiki/Time_constant#Time_constants_in_electrical_circuits
https://en.wikipedia.org/wiki/Multivibrator#Monostable

I think the circuit in post #20 is more simple and clear using 555 ic

Not counting things like decoupling caps, the #20 circuit has 2 chips and 6 passive components, while the #21 circuit has 1 chip and 2 passives plus one small signal transistor.

The 555 has the benefit of an extra-beefy output stage so it doesn't need an added driver transistor. However, the 555 is not a true monostable - it has no positive feedback to disable the input during and after the timing period, and disabling the input is required per post #1. That is the reason it needs R1, R2, and C3. It also needs a 14 pin chip just for the one NAND gate.

When you add in power supply decoupling capacitors:

555: 2 chips, 27 soldered pins

4093: 1 chip, 23 soldered pins

ak

 

Can be done with 1 LMC555.

 

I don't think R1 is needed in the circuit in post 20.

That resistor should only be needed if the timer is triggered with a NO pushbutton or an open collector.

 

I don't think R1 is needed in the circuit in post 20.

Agree.

 

Can be done with 1 LMC555.

If either input goes low during the timing period, the timer is disrupted; not completely reset, but unable to finish its period correctly because C1 will start discharging through R2 rather than continue charging through R1.

ak

 

If either input goes low during the timing period, the timer is disrupted; not completely reset, but unable to finish its period correctly because C1 will start discharging through R2 rather than continue charging through R1.
ak

Depending on how long both Q5 outputs are high. I changed the component values for R1,R2 and C1.
It requires appx 1 ms to get sufficient charge for a 3 second delay.
However if both inputs remain high for an extended period that will prolong the timing cycle but don't see that making much difference with a 15hz clock. And the TS also stated: "If the 2 outputs match for a long period of time, they can trigger the alarm repeatedly for a 3 second period, until they no longer match."

 

View attachment 327351
Only included 1 LED because description is vague.
Even harder for us to implement...

yes, but it seems that you have hit the nail on the head. I thank you for this!! I also thank all the other replies for their help!!

 

If either input goes low during the timing period, the timer is disrupted; not completely reset, but unable to finish its period correctly because C1 will start discharging through R2 rather than continue charging through R1.

ak

View attachment 327368

Thank you so much Analogue Kid, I truly appreciate your help!!

 

Depending on how long both Q5 outputs are high. I changed the component values for R1,R2 and C1.
It requires appx 1 ms to get sufficient charge for a 3 second delay.
However if both inputs remain high for an extended period that will prolong the timing cycle but don't see that making much difference with a 15hz clock. And the TS also stated: "If the 2 outputs match for a long period of time, they can trigger the alarm repeatedly for a 3 second period, until they no longer match."
View attachment 327371

 

Thank you so much for your help!!

Depending on how long both Q5 outputs are high. I changed the component values for R1,R2 and C1.
It requires appx 1 ms to get sufficient charge for a 3 second delay.
However if both inputs remain high for an extended period that will prolong the timing cycle but don't see that making much difference with a 15hz clock. And the TS also stated: "If the 2 outputs match for a long period of time, they can trigger the alarm repeatedly for a 3 second period, until they no longer match."
View attachment 327371

Thank you so much for your helpful reply.

 

First pass at a schematic as described in #18.

R1-C1 are the monostable timing components. Their values are approximate because the input transition voltage levels in the 4093 are not tightly controlled in fabrication.

When both Y5 output are high (even for a few nanoseconds), U1A goes low and triggers the monostable. While it is timing, feedback from pin 10 to pin 11 prevents extra input activity from re-triggering the timer. The output is inverted in U1B to get the correct logic polarity for Q1.

A potential problem is that the 4017 outputs sometimes have very short glitches caused by the way the outputs are decoded from a shift register. To prevent these from creating false triggers, add a small R-C filter at U1A pins 1 and 2. 0.1 uF and 1.0 K should work.

ak

View attachment 327352

Thank you so much for your interesting answer. I do appreciate it!

 

yes, but it seems that you have hit the nail on the head. I thank you for this!! I also thank all the other replies for their help!!

You're welcome.

If you're hung up about the number of ICs, you can replace the NAND gate with a discrete version:

Q1 = BC547, diodes 1N4148

With BC547, you want base current to be Ic/20 (for 2N3904 the ratio would be 10). With a 9V supply, I'd increase R1 to 2k and make R2 30k.

As mentioned previously, R1 in the timer circuit I posted is unnecessary.

 

You're welcome.

If you're hung up about the number of ICs, you can replace the NAND gate with a discrete version:
View attachment 327401
Q1 = BC547, diodes 1N4148

With BC547, you want base current to be Ic/20 (for 2N3904 the ratio would be 10). With a 9V supply, I'd increase R1 to 2k and make R2 30k.

As mentioned previously, R1 in the timer circuit I posted is unnecessary.

you are kidding!!!...Holy Crap!!!!! this circuit is so simple!!!!...I thought the 555 ones were simple, but this one is amazing!!!! Im prototyping this immediately to watch its operation!!!!! (im also making the 555 ones as well, just out of curiosity!!)

 

you are kidding!!!...Holy Crap!!!!! this circuit is so simple!!!!...I thought the 555 ones were simple, but this one is amazing!!!! Im prototyping this immediately to watch its operation!!!!! (im also making the 555 ones as well, just out of curiosity!!)

 

does this need the 555 as a 3 second timer on the "Out" tho?

 

does this need the 555 as a 3 second timer on the "Out" tho?

It still needs the timer. The circuit in #35 just replaces the CMOS NAND gate with a discrete version.

With D1 or D2 removed, it becomes an inverter. Add more diodes and it becomes a NAND gate with more inputs.

 

you are kidding!!!...Holy Crap!!!!! this circuit is so simple!!!!...

Hang on there, sparky. The circuit in #35 is not a complete solution. It replaces a small portion of the circuit in #20.

ak