Digital Counting Circuit Using 4026 Counters

Thread Starter

aac044210

Joined Nov 19, 2019
178
Hi:

Is it necessary to use 220Ω current limiting resistors when using 4026 counters and common cathode displays?
Also, is it true that you don't need to use a decoder/driver chip?

1604604700246.png

Thanks
 

dl324

Joined Mar 30, 2015
13,082
Is it necessary to use 220Ω current limiting resistors when using 4026 counters and common cathode displays?
It's worse than that. The outputs are only guaranteed to source 1.6mA with a 5V supply (which you didn't provide). You'd be trying to get closer to 10mA with a 220 ohm resistor.
Also, is it true that you don't need to use a decoder/driver chip?
From the first paragraph in the TI/Harris/RCA datasheet:
clipimage.jpg

Display drive circuit recommendations:
clipimage.jpg
 

Ian0

Joined Aug 7, 2020
3,186
I've seen the 4026 used with no resistors, using the CMOS's inherent current limiting.
1mA will light up a modern high-efficiency 7-segment display nicely.
 

AnalogKid

Joined Aug 1, 2013
9,351
Read the datasheet (!!!) for the Output High (Source) Current. The typical value for a 5 V rail circuit is 1 mA for a normal output voltage. It can supply 3.2 mA, but the output voltage sags by 50%. This indicates that you are stressing the output stage by pulling it into a "non-saturated" condition where the output transistors heat up. Not good. At this point the channel resistance of the output FETs is acting as the current limiting resistors. This is not a sound practice.

ak
 

Ian0

Joined Aug 7, 2020
3,186
This is not a sound practice.
Whyever not? FETs are used in linear mode all the time. Have you never made a crystal oscillator with a 4069UB or 74HCU04?
See page 17 of https://worldradiohistory.com/Archive-Electronics-Today/ETI-Electronic-Circuit-Design-No-1.pdf
"Now we will have to consider the interfacing of displays with our seven segment counters. LEDs like the MAN -3 which have a low current will interface directly with the outputs of the 4026A or 4033A and give a tolerable brightness with the available drive current (about 5mA), provided that Vdd is more than 9V"
 

dl324

Joined Mar 30, 2015
13,082
I checked the website the schematic is attributed to. I couldn't find any schematics, but the author is clearly unqualified to be designing circuits.

The circuit being discussed would be an embarrassment to anyone with any training in the field. Loaded outputs and no debouncing for the clock switch.
 

AnalogKid

Joined Aug 1, 2013
9,351
I checked the website the schematic is attributed to. I couldn't find any schematics, but the author is clearly unqualified to be designing circuits.

The circuit being discussed would be an embarrassment to anyone with any training in the field.
Completely agree.
Loaded outputs and no debouncing for the clock switch.
*OVER*-loaded outputs.

ak
 

AnalogKid

Joined Aug 1, 2013
9,351
Whyever not? FETs are used in linear mode all the time. Have you never made a crystal oscillator with a 4069UB or 74HCU04?
Where the output and/or crystal currents are so high that the output voltage sags by 50%? - No. Not ever.

And yes, I have experience with using CMOS inverters as linear amplifiers. Back in the 70's I designed and built a complete stereo preamp using nothing but CMOS inverters, including the phono preamp with equalization and Baxandall tone controls. Not the highest fi in the world, but it proved the concept for lab work in an EE course.

ak
 

dl324

Joined Mar 30, 2015
13,082
I am a mere hobbyist but I think that a large proportion of the circuits etc. on the internet
are probably garbage.
There is an endless supply of people who think they know more than they do. That's unfortunate for the people who don't know enough to separate the wheat from the chaff.

You should learn to read datasheets.
 

Ian0

Joined Aug 7, 2020
3,186
Where the output and/or crystal currents are so high that the output voltage sags by 50%? - No. Not ever.
So how do you think that the output get biassed to half supply? Could it possibly be that the N-channel FET is pulling the output down to that level? So you have not one but two FETs dissipating with half-supply across drain and gate? And you think that's better than just one? Presumably, you've never measured how much current a CMOS gate takes when biassed into linear mode.
 

Ian0

Joined Aug 7, 2020
3,186
You should learn to read datasheets.
SO let's look at the datasheet.
Here's the list of maximum ratings. Do you see a maximum current specification for the output? Do you see a line on the output current graph that specifies the maximum current? There isn't one. So do you think Harris simply forgot to include it and it's gone unnoticed for the best part of 50 years? No - there is no maximum output current specification, only a maximum power dissipation.
Let's say you have a 5V supply and 1.8V LED. The output current will be about 5mA. That's 3.2x5mA x7segments dissipation in the IC = 112mW, well within the 500mW limit. So who says it's overloaded? - DL324 and AnalogKid might, but the manufacturer doesn't.

In the words of the late Bob Pease “show me where it says I can’t”.
 

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AnalogKid

Joined Aug 1, 2013
9,351
In the words of the late Bob Pease “show me where it says I can’t”.
Hold on there, sparky. I knew Bob Pease. I (very friendly) argued with Bob Pease about open loop gain in a closed loop system. You are no Bob Pease.
Here's the list of maximum ratings.
No, it isn't. That is a table of **Recommended** operating conditions. It says so in the title.

The "Absolute Maximum" ratings are on page 1 of the datasheet.

ak
 

AnalogKid

Joined Aug 1, 2013
9,351
AND - let's look at the chart in post #16 for a Vgs of -5 V, which is very close to the typical internal drive voltage when the chip is powered by 5 V. Note that when the output current is 4.2 mA, the output voltage (Vdd - Vds) is not 5 V, not 4 V, nor 3 V ... In fact, that supposed "high" output voltage is actually at ground. That is, with a true current source as a load (remember, this is lab validation testing that reveals the limits of device function, not a typical operating environment), a 4.2 mA load current causes the output voltage to sag from a typical value of 4.95 V all the way down to 0 V.

So the question is this - even if the datasheet does not specifically prohibit operating in this condition, why would a circuit designer want to? Does this really smell to you like a competent design optimized for long-term reliability?

ak
 

Ian0

Joined Aug 7, 2020
3,186
So the question is this - even if the datasheet does not specifically prohibit operating in this condition, why would a circuit designer want to?
To save space and cost; because it operates the device inside its maximum limits, and because the actual value of the output current really does’t matter too much,
Does this really smell to you like a competent design optimized for long-term reliability?
Perfectly. I have used 4000 series CMOS many times with no current limiting resistors, in designs which have sold in the thousands with no reliability problems. I see them on eBay 20+ years old and still working.
 
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