It's worse than that. The outputs are only guaranteed to source 1.6mA with a 5V supply (which you didn't provide). You'd be trying to get closer to 10mA with a 220 ohm resistor.Is it necessary to use 220Ω current limiting resistors when using 4026 counters and common cathode displays?
From the first paragraph in the TI/Harris/RCA datasheet:Also, is it true that you don't need to use a decoder/driver chip?
Whyever not? FETs are used in linear mode all the time. Have you never made a crystal oscillator with a 4069UB or 74HCU04?This is not a sound practice.
Completely agree.I checked the website the schematic is attributed to. I couldn't find any schematics, but the author is clearly unqualified to be designing circuits.
The circuit being discussed would be an embarrassment to anyone with any training in the field.
*OVER*-loaded outputs.Loaded outputs and no debouncing for the clock switch.
Where the output and/or crystal currents are so high that the output voltage sags by 50%? - No. Not ever.Whyever not? FETs are used in linear mode all the time. Have you never made a crystal oscillator with a 4069UB or 74HCU04?
I am a mere hobbyist but I think that a large proportion of the circuits etc. on the internetCompletely agree.
*OVER*-loaded outputs.
ak
So the outputs should have a driver transistor for each segment?Completely agree.
*OVER*-loaded outputs.
ak
Yes. Trust the datasheet. It has example circuits for both CA and CC LED displays.So the outputs should have a driver transistor for each segment?
There is an endless supply of people who think they know more than they do. That's unfortunate for the people who don't know enough to separate the wheat from the chaff.I am a mere hobbyist but I think that a large proportion of the circuits etc. on the internet
are probably garbage.
thanksYes. Trust the datasheet. It has example circuits for both CA and CC LED displays.
ak
Thanks.There is an endless supply of people who think they know more than they do. That's unfortunate for the people who don't know enough to separate the wheat from the chaff.
You should learn to read datasheets.
So how do you think that the output get biassed to half supply? Could it possibly be that the N-channel FET is pulling the output down to that level? So you have not one but two FETs dissipating with half-supply across drain and gate? And you think that's better than just one? Presumably, you've never measured how much current a CMOS gate takes when biassed into linear mode.Where the output and/or crystal currents are so high that the output voltage sags by 50%? - No. Not ever.
SO let's look at the datasheet.You should learn to read datasheets.
Hold on there, sparky. I knew Bob Pease. I (very friendly) argued with Bob Pease about open loop gain in a closed loop system. You are no Bob Pease.In the words of the late Bob Pease “show me where it says I can’t”.
No, it isn't. That is a table of **Recommended** operating conditions. It says so in the title.Here's the list of maximum ratings.
Seems like I’m cropped the wrong bit off the scan.The "Absolute Maximum" ratings are on page 1 of the datasheet.
To save space and cost; because it operates the device inside its maximum limits, and because the actual value of the output current really does’t matter too much,So the question is this - even if the datasheet does not specifically prohibit operating in this condition, why would a circuit designer want to?
Perfectly. I have used 4000 series CMOS many times with no current limiting resistors, in designs which have sold in the thousands with no reliability problems. I see them on eBay 20+ years old and still working.Does this really smell to you like a competent design optimized for long-term reliability?
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by Jake Hertz
by Duane Benson
by Jake Hertz
by Duane Benson