# Closed loop stedy-state error in simple RC circuit; spice simulation not matching expected result

#### Elerion

Joined Sep 11, 2017
125
Hello everyone.

This question is about control theory, closed-loop responde and a simple RC circuit.

We start from a simple low pass RC, with a single pole at 10 rad (approx 1.59 Hz). E.g. 1 uF and 100 kohm.
Time constant is 0.1 s, so the capacitor charges up in about half a second. So far so good.

Transfer function is:
1
---------
0.1 s + 1

Now, use unity negative feedback.
The closed loop transfer function (A/1+A) ) is:

0.1 s + 1
--------------------
0.01 s^2 + 0.3 s + 2

This system is type 0 (no poles at the origin), so there'll be a finite error to a step input. In this case, a 50% error. And, if we simulate the circuit using Spice software, a 1 V input produces a 0.5 V output, which is expected.

This is where I'm having trouble:
To reduce the error to 10%, theory tells us to add a 10x gain to the open loop transfer function.
If we simulate in matlab/octave, we can see this is true.
BUT, a Spice simulation doesn't match. I get a 25% error instead.

Attached, screenshots and LTSpice circuit, and matlab/octave simple script.
In red, simple RC circuit open loop. In black, closed loop RC circuit with 10x gain. Both, for matlab/octave and LTSpice.

What am I missing?
Thanks.

#### Attachments

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Joined Mar 10, 2018
4,057
When you sim im Mtalab/Octave you are doing a small signal analysis, which
does not account for slew rate limiting in large signal response, experienced
by the second stage ?

And most data sheet specs at +/- 10V supply, at 5V supply that aggravates the
performance characteristics.

Just a thought.

Regards, Dana.

#### Veracohr

Joined Jan 3, 2011
765
It's because of the relative resistance of R1 and R2 (designators in your simulation). See here the difference when changing R2 from 10k to 1Meg, keeping everything else the same:

#### Elerion

Joined Sep 11, 2017
125
It's because of the relative resistance of R1 and R2 (designators in your simulation). See here the difference when changing R2 from 10k to 1Meg, keeping everything else the same:
View attachment 156653
Yes, that was it.
Thank you very much.

It was not obvious to me.
I initially thought that the feedback loop would compensate for changes in the output, but I just oversimplified the whole thing.

Joined Mar 10, 2018
4,057
When you select hi Z Rs, especially fdbk R, you create another pole
of consequence due to stray C at NI input to OpAmp.

http://www.ti.com/lit/an/sloa013a/sloa013a.pdf

Hi Zs do not solve everything, they bring their own baggage, including more
noise.

Regards, Dana.