I've just spent a couple of hours building the main circuit up on a breadboard and cannot find anything wrong with it. It's working fine here for me. I used the capacitor, diode, resistor coupling setup, as per the later stages, to trigger the Delay 1 stage to give me a shorter pulse than that of the delay itself, though that doesn't affect the rest of the circuit. I didn't add the 2 pulse output timers since I don't have any more 555's!
I enclose a scope shot below.



The outputs are in order:
Yellow, Delay 1
Purple, Timer 1
Blue, Delay 2
Green, Timer 2

 

@Sarah, please explain the function of the diodes between the input and the V+ line. It looks to me like they short out the input pulse.

 

Wrong tag MB.

JFTR those diodes prevent overvoltage on the trigger line.

 

So, I also spent some time trying to find a problem with the circuit but in LTSpice not a BB as per Sarah (kudos to her).

So now the OP has conformation that the circuit will work in physical form as well as a sim and can now take the suggestions that there is an error in the build or perhaps something like faulty chips.

 

@Sarah, please explain the function of the diodes between the input and the V+ line. It looks to me like they short out the input pulse.

If we assume the input (left hand side) of the coupling capacitor is normally at 0V, and its right side is charged to V+ by the pull-up resistor, when the input pulse goes high, the right side tried to go to approximately twice V+. The diode clamps the spike to V+ plus 0.7V.
When the input falls, the right hand side initially goes low, but then charges to V+ again at the CR time constant, producing the required negative going trigger pulse in our case. If it was a grounding push button on the left hand side, and normally pulled high, it would still work the same way.

 

I looked in the Signetics Linear application manual, 1973 version. It shows a string of 555 timers quite similar EXCEPT for the diodes from the input to the V+ line, and the resistor from the input to the V+ line is 27K not 10K. Certainly that diode provides a short circuit for the trigger pulse rising edge. Really, what was it's intended function?? I see no benefit of it at all. If the intent is to assure a uniform start up condition, that can be provided by the RESET inputs to pin #1
For the diode "OR" function driving "V cyl" I suggest an actual OR gate and a driver thransistor, providing better isolation.

The 10k pull-up resistors can be replaced with 27k.

As for the diodes, Brain (Super Moderator at edaboard.com) commented:
Look at the 10nF capacitors at the output of the first, second and third and fourth ICs, when the output of the NE555 is low, they charge to 10V through the following 10K pull-up resistor. When the output of a 555 goes high, it lifts the driven side of the capacitor high so momentarily the 10K side rises to about 20V and could damage the following IC or cause operational problems.
And practically yes, without the diodes the voltage at trigger pin rises about 20V momentarily.

Actual OR gate can be considered but first the main issue is resolved, provided that it is not the cause of the problem.

 

So, I also spent some time trying to find a problem with the circuit but in LTSpice not a BB as per Sarah (kudos to her).

So now the OP has conformation that the circuit will work in physical form as well as a sim and can now take the suggestions that there is an error in the build or perhaps something like faulty chips.

View attachment 322989

Hmm, so my doubt is seconded.
I have about 10 pcs of NE555. I will try replacing them otherwise, will order some new pieces and get back.

Thank you all of you, for your inputs; particularly Sarah for sparing her time for physical checking on breadboard.

 

As for the diodes, Brain (Super Moderator at edaboard.com) commented:
Look at the 10nF capacitors at the output of the first, second and third and fourth ICs, when the output of the NE555 is low, they charge to 10V through the following 10K pull-up resistor. When the output of a 555 goes high, it lifts the driven side of the capacitor high so momentarily the 10K side rises to about 20V and could damage the following IC or cause operational problems.
And practically yes, without the diodes the voltage at trigger pin rises about 20V momentarily.

I think he's worried about nothing.

From the National Semiconductor schematic there are 3 base-emitter junctions, a diode (CB junction from PNP) and a 1k resistor in series:

Since the maximum supply voltage is 16V, I doubt that any of the base-emitter junctions are going to be broken down hard enough (if any breakdown at all) to cause any damage. With a 10V supply, I see nothing to worry about. That's probably why Signetics didn't mention clamping when they described AC coupling the trigger.

 

Wrong tag MB.

JFTR those diodes prevent overvoltage on the trigger line.

The only potential over voltage source would be the coil in the solenoid, in which case the diodes should be on the output of the driver stage and not on the input to the next stage.

 

Delay 1 is only 7.5 ms, which is so short that it raises the question, Why bother? It is way shorter than most person's ability to hit a pushbutton switch and release quickly. That means that the actual output pulse width will be stretched my several hundred percent while the operator's finger rests on the button. IOW the actual Delay1 period is however long the button is pressed plus 7.5 ms.

Why is there a 10 micro-ohm resistor in series with each power supply decoupling capacitor? Note that there are only two decoupling capacitors, but each 555 requires one.

Also, the debounce time constant is less than 400 microseconds, which is way too short for most switches. The extra-short debounce time constant means that Timer1 could see a burst of multiple pulses from Delay1.

Both the Rev and Fwd pulses are very close to a 50/50 duty cycle. Thus, the six 555s can be replaced with one hex inverter. If you reduce the system power to 5 V, a 74AC14 should do it.

And IIRC, the original 555 was built on a linear 60 V process line, not their bipolar logic line.

ak

 

At this point we still know nothing about the intent of the circuit. With one exception, all resistor values are +/-1-% tolerance. Interestingly, the exception is a 1% tolerance value, which seems a waste given that it is combined with such low tolerance resistor and capacitor.

Can the TS supply the intended values for Delay1 and 2, Timer1 and 2, and Pulses1 and 2? Also, the required accuracy / precision / tolerance.

ak

 

I think he's worried about nothing.

From the National Semiconductor schematic there are 3 base-emitter junctions, a diode (CB junction from PNP) and a 1k resistor in series:
View attachment 323021
Since the maximum supply voltage is 16V, I doubt that any of the base-emitter junctions are going to be broken down hard enough (if any breakdown at all) to cause any damage. With a 10V supply, I see nothing to worry about. That's probably why Signetics didn't mention clamping when they described AC coupling the trigger.

You're right in this case with the circuit running from a 10V supply, but what if it was run at the maximum rating for a bipolar 555, or a CMOS one. The diode is standard clamping circuitry for capacitor coupling of logic type signals to prevent overvoltage breakdown of gate inputs. It's safer than relying on internal clamping methods which may or may not exist in all cases, and it ensures a clean pulse.

 

Delay 1 is only 7.5 ms, which is so short that it raises the question, Why bother? It is way shorter than most person's ability to hit a pushbutton switch and release quickly. That means that the actual output pulse width will be stretched my several hundred percent while the operator's finger rests on the button. IOW the actual Delay1 period is however long the button is pressed plus 7.5 ms.

Why is there a 10 micro-ohm resistor in series with each power supply decoupling capacitor?

Also, the debounce time constant is less than 400 microseconds, which is way too short for most switches. The extra-short debounce time constant means that Timer1 could see a burst of multiple pulses from Delay1.

Both the Rev and Fwd pulses are very close to a 50/50 duty cycle. Thus, the six 555s can be replaced with five sections of one hex inverter. If you reduce the system power to 5 V, a 74AC14 should do it.

And IIRC, the original 555 was built on a linear 60 V process line, not their bipolar logic line.

ak

I found this short delay to be a problem with my breadboard testing also. I was using a cheap Aliexpress PWM module which only goes down to 1Hz and 1% pulse width, and even this was stretching the Delay 1 output longer than it should be, So I added a 4n7 capacitor plus 10k//diode to V+ arrangement to the trigger of Delay 1. The result is seen in the scope shot.

Later I tried it with the switch circuitry, just out of curiosity. It bounced like crazy!

 

Disclaimers: This is a first-pass at a concept. It does not have any of the LED indicators. I squirted this out late last night. Is that enough qualifiers?

The overall circuit is four pulse-formers in series, with two of them gating oscillators. Because each one is triggered by the falling edge of the previous one, a single inverter restores the logic polarity at each stage. There are only two capacitor values in this design, as opposed to six in the original.

The original circuit has the Pulse (oscillator) outputs low in the disabled state. Working backwards from there required changing the logic polarity of the start switch.

If you really need 10 V operation, the 74AC14 can be replaced with a CD40106 (same pinout). However, the 14 has a much beefier and "stiffer" output stage, so the pulse former reset times (for example, when C2 is discharging through D3) might be a bit longer with the 106. This also might be an issue with the two oscillator outputs, since we do not know the output current requirements for them

NOTE: All time constants are based on in-my-head estimates of the original schematic. I'm sure some adjusting is necessary. Also, this concept uses parts already in my design libraries. Some component properties such as power or tolerance probably are not required.

ak

 

You're right in this case with the circuit running from a 10V supply, but what if it was run at the maximum rating for a bipolar 555, or a CMOS one.

I mentioned the 16V maximum operating voltage for NE555. That happens to be about the voltage required to break down 3 junctions and conduct through a diode and the 1k resistor, so I still don't think there's any risk. If junctions broke down, the reverse current wouldn't be high enough to damage them (heating is the issue as I recall).

The diode is standard clamping circuitry for capacitor coupling of logic type signals to prevent overvoltage breakdown of gate inputs. It's safer than relying on internal clamping methods which may or may not exist in all cases, and it ensures a clean pulse.

OP is using the bipolar version, so no gate inputs or clamping diodes involved. In CMOS parts, the ESD protection/clamping diodes can handle on the order of 10-100mA and I think the primary issue is latchup or electromigration in the metallization.

 

I mentioned the 16V maximum operating voltage for NE555. That happens to be about the voltage required to break down 3 junctions and conduct through a diode and the 1k resistor, so I still don't think there's any risk. If junctions broke down, the reverse current wouldn't be high enough to damage them (heating is the issue as I recall).
OP is using the bipolar version, so no gate inputs or clamping diodes involved. In CMOS parts, the ESD protection/clamping diodes can handle on the order of 10-100mA and I think the primary issue is latchup or electromigration in the metallization.

I have to admit, I mostly add the diode so that I can be sure that the ensuing pulse is going to be the shape I need it and reach the full amplitude of whichever direction it's going.

 

I suspect D4 from the original schematic (diode on the output of Timer2) is either shorted or backwards. It's the only component that can make both of these statements true:

a) If TIMER2 is present, there will be no output at DELAY2. (H-Cyl LED doesn't light up). This is my problem.
b) If TIMER2 is removed, DELAY2 will give output and H-Cyl LED would light up. Interestingly, PULSES2 also generates pulses though without TIMER2.

While not triggered, Timer2 would hold Dir low through D3 (diode on the output of Timer1) and prevent triggering Delay2. Without Timer2 in the circuit it, it is not pulling Dir down and allows Delay2 to function. It shouldn't be possible for Pulses2 to trigger without Timer2 but it does because it is getting coupled to Dir.

 

I suspect D4 from the original schematic (diode on the output of Timer2) is either shorted or backwards. It's the only component that can make both of these statements true:

Well, I just ran the sim again and sure enough shorting or reversing D4 causes symptoms pretty close to what the OP is experiencing.

 

Delay 1 is only 7.5 ms, which is so short that it raises the question, Why bother? It is way shorter than most person's ability to hit a pushbutton switch and release quickly. That means that the actual output pulse width will be stretched my several hundred percent while the operator's finger rests on the button. IOW the actual Delay1 period is however long the button is pressed plus 7.5 ms.

Why is there a 10 micro-ohm resistor in series with each power supply decoupling capacitor? Note that there are only two decoupling capacitors, but each 555 requires one.

Also, the debounce time constant is less than 400 microseconds, which is way too short for most switches. The extra-short debounce time constant means that Timer1 could see a burst of multiple pulses from Delay1.

Both the Rev and Fwd pulses are very close to a 50/50 duty cycle. Thus, the six 555s can be replaced with one hex inverter. If you reduce the system power to 5 V, a 74AC14 should do it.

And IIRC, the original 555 was built on a linear 60 V process line, not their bipolar logic line.

ak

You can use a DC4049 hex inverter that is quite happy with 12 or 15 volts. AND cocts less AND has a better pin-out.

 

Assuming you meant to say CD4049 rather than DC4049 . . .

The CD4049 does not have Schmitt trigger inputs, so it will not work well for the pulse formers and will not work at all for the oscillators shown in post #34. Also, it is in an arguably non-standard package (for a hex inverter) and a really non-standard pinout (Vdd placement and gate pin assignments).

Surprisingly, the 4049 has faster transitions times and better output current capability then the 40106, although nothing like an AC series part. Still, without Schmitt trigger inputs I don't see how a single chip could perform all of the circuit functions.

ak