Cascaded 555s behaving strangely

dl324

Joined Mar 30, 2015
17,142
Post the information on this site and explain what the issue is.

The symbol being use is terrible at conveying circuit intent:
1716325828372.png
 

MisterBill2

Joined Jan 23, 2018
19,461
In addition to showing us a wiring diagram, an explanation describing what it is intended to do,and a description of what it is doing instead, will help some of us quickly see the problem. Not me, but there are a few MASTERS OF the %%% timer around.
 

Thread Starter

abuhafss

Joined Aug 17, 2010
317
I posted the link intentionally bcz of past bitter experience. Long ago, I shared a problem on two different forums. I got strong reaction from the moderators that I should have posted the link instead.

Here is the revised schematic.
1716374213333.png
The flow of the circuit is as follows:

a) When the push button is pressed, DELAY1 (monostable 555) would cause a delay.
b) After the delay, TIMER1 monostable 555) gets triggered thru 10nF. TIMER1 would power on PULSES1 (astable 555) for a duration set by TIMER1.
c) When the TIMER1 duration is completed, PULSES1 gets off and DELAY2 is triggered thru 10nF.
The lower 3 x 555 are almost copy of the upper 3 x 555.
e) DELAY2 causes a delay then triggers TIMER2.
f) TIMER2 switches on PULSES2, which generates pulses.

Theoretically the circuit seems OK, simulation is also OK. But physically on PCB, I am facing some problems:

a) If TIMER2 is present, there will be no output at DELAY2. (H-Cyl LED doesn't light up). This is my problem.
b) If TIMER2 is removed, DELAY2 will give output and H-Cyl LED would light up. Interestingly, PULSES2 also generates pulses though without TIMER2.

I know, all this can be done with easily an 8-pin microcontroller and I had done it. But the current project is limited to 555s.
 
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Thread Starter

abuhafss

Joined Aug 17, 2010
317
1716374861373.png
Pin 2 of DELAY2, when TIMER2 is present.

1716374932134.png
Pin 2 of DELAY2 when TIMER2 is removed.

These might give some clue for the abnormal performance.
 

dl324

Joined Mar 30, 2015
17,142
Long ago, I shared a problem on two different forums. I got strong reaction from the moderators that I should have posted the link instead.
You shouldn't have gotten a complaint from moderation on this site because they prefer to not have broken links when threads are referenced in the future.
a) If TIMER2 is present
What does present mean? The IC is physically installed in the board? Or the output is HIGH?

I find it difficult to read schematics with a black background.
cascadedTimers.jpg
 

Thread Starter

abuhafss

Joined Aug 17, 2010
317
I have mentioned two conditions i.e. IC present and IC removed.
This means, IC is present in its base or it is removed.

Extremely, sorry for the black background . I just copied it from the simulator, I should have changed the background.
 

dl324

Joined Mar 30, 2015
17,142
I have mentioned two conditions i.e. IC present and IC removed.
This means, IC is present in its base or it is removed.
The presence of TIMER2 shouldn't have any effect on the output of DELAY2. TIMER1 triggers DELAY2 which triggers TIMER2.

Other than different delays and frequency, the "2" cascade is the same as the "1". Have you verified that things are wired correctly and that there is no board defect?

10nF should be sufficient for AC coupling the trigger from DELAY2 but what was the reason that you used 100nF for the trigger to DELAY1?
 
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Thread Starter

abuhafss

Joined Aug 17, 2010
317
The presence of TIMER2 shouldn't have any effect on the output of DELAY2. TIMER1 triggers DELAY2 which triggers TIMER2.

Other than different delays and frequency, the "2" cascade is the same as the "1". Have you verified that things are wired correctly and that there is no board defect?

10nF should be sufficient for AC coupling the trigger from DELAY2 but what was the reason that you used 100nF for the trigger to DELAY1?
Yes, TIMER2 shouldn't affect the output of DELAY2 bcz the former is activated by the latter. But physically it is being effected as there is no output of DELAY2 when TIMER2 is in circuit.
Moreover, I could not understand why the PULSES2 generates pulses when TIMER2 is absent.
Yes, both the cascades are identical and all connections are fine.
All the AC coupling capacitors were changed 10nF. (Sorry missed in the schematic).
 

dl324

Joined Mar 30, 2015
17,142
Yes, TIMER2 shouldn't affect the output of DELAY2 bcz the former is activated by the latter. But physically it is being effected as there is no output of DELAY2 when TIMER2 is in circuit.
Try triggering DELAY2 manually and see if you can capture its output pulse while monitoring the output of TIMER2. If you have difficulty doing that, use a timer to make an astable to keep retriggering DELAY2 so you can see why it isn't working.
Moreover, I could not understand why the PULSES2 generates pulses when TIMER2 is absent.
With reset on PULSES2 not being driven, the outputs of DELAY1 and TIMER1 can enable the PULSES2 astable. A sufficiently low value pull-down resistor would prevent that.
 
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ElectricSpidey

Joined Dec 2, 2017
2,885
It's not surprising that the pulse 555 runs with its reset pin open, have a look at the internals and you will get the clue you need.

Also, if you look in the datasheet the voltage needed to pull the 555 into reset could be as low as .3 volts or as high as 1 volt, and the only path I see to ground with Timer 2 removed has an LED and a diode in series with it...if I am reading the schematic correctly.

None of the other timers can drive the reset pin high due to D3 in the upper schematic which has no descriptor in the lower one.
 
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Thread Starter

abuhafss

Joined Aug 17, 2010
317
Try triggering DELAY2 manually and see if you can capture its output pulse while monitoring the output of TIMER2. If you have difficulty doing that, use a timer to make an astable to keep retriggering DELAY2 so you can see why it isn't working.
Manual triggering DELAY2 shows output on its pin 3. But after the delay, TIMER2 does not get triggered.
 

Thread Starter

abuhafss

Joined Aug 17, 2010
317
the only path I see to ground with Timer 2 removed has an LED and a diode in series with it...if I am reading the schematic correctly.

None of the other timers can drive the reset pin high due to D3 in the upper schematic which has no descriptor in the lower one.
Yes, you have read the schematic correctly.
I couldn't pull it down with 1K. I am trying with lower values.
 

dl324

Joined Mar 30, 2015
17,142
Manual triggering DELAY2 shows output on its pin 3. But after the delay, TIMER2 does not get triggered.
Monitor the falling edge of the output of DELAY2 on the other side of the AC coupling cap to verify whether that node is dropping to VCC/3.
 

MisterBill2

Joined Jan 23, 2018
19,461
I looked in the Signetics Linear application manual, 1973 version. It shows a string of 555 timers quite similar EXCEPT for the diodes from the input to the V+ line, and the resistor from the input to the V+ line is 27K not 10K. Certainly that diode provides a short circuit for the trigger pulse rising edge. Really, what was it's intended function?? I see no benefit of it at all. If the intent is to assure a uniform start up condition, that can be provided by the RESET inputs to pin #1
For the diode "OR" function driving "V cyl" I suggest an actual OR gate and a driver thransistor, providing better isolation.
 
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