All About Circuits

Cascaded logarithmic amplifier offset

Search Forums New Posts
L

Thread Starter

lucasN6676

Joined Feb 20, 2024
18
Hello everyone, I am simulating an RF power detector (RMS power detector followed by a cascaded logarithmic amplifier). I want to reduce the offset from the cascaded logarithmic amplifier, so I used the chopper technique. However, how can I account for the effect of the clock on the switches when I run harmonic balance in cadence?
The circuit is like the circuit in this paper.
 

Attachments

You must log in or register to reply here.
Thread starter Similar threads Forum Replies Date
Vilius_Zalenas Unwanted ringing in cascaded Sallen-Key filter amplifier Analog & Mixed-Signal Design 8
B 40 LED Cascaded Decade Counter Digital Design 60
L Cascaded logarithmic amplifier offset Wireless & RF Design 1
abuhafss Cascaded 555s behaving strangely Digital Design 41
javegab2173 Decentralized control for series cascaded PV inverters - PSIM Simulation Homework Help 0
Similar threads
Unwanted ringing in cascaded Sallen-Key filter amplifier
40 LED Cascaded Decade Counter
Cascaded logarithmic amplifier offset
Cascaded 555s behaving strangely
Decentralized control for series cascaded PV inverters - PSIM Simulation

You May Also Like

Top