Hello everyone, I am simulating an RF power detector (RMS power detector followed by a cascaded logarithmic amplifier). I want to reduce the offset from the cascaded logarithmic amplifier, so I used the chopper technique. However, how can I account for the effect of the clock on the switches when I run harmonic balance in cadence?
Attached below, a paper of a similar design

 

The operation of cascode (two in series) log function amplifiers is not likely to work under most conditions. The slightest bit of DC offset will cause serious problems, and anything close to stable operation is not likely. The models may work but the hardware will have problems.