Purpose of the ckt is to generate high voltage pulses without damaging the fet.

50vdc power supply. - side to 87.7 mh (19.4 ohms) coil and the other end of the coil to Drain and stubber diode.. Source to +50vdc. Gate controlled by Signal generator square wave 10v peak to peak through 1K resistor paralled through 10K resistor to +50vdc. Using IXTH48P20P P Channel MOSFET

Using signal generator controls varying offset of square wave from -20 to +20 volts. no reaction. varying Pulse Width from 10% to 100% No reaction.

 

Welcome to AAC!

Post a schematic.

 

You have the generator output connected to the gate via a resistor. Where is the other wire from the generator connected?

 

You have the generator output connected to the gate via a resistor. Where is the other wire from the generator connected?

You have the generator output connected to the gate via a resistor. Where is the other wire from the generator connected?

Negative side of 50vdc power supply.

 

A circuit really is needed. By what you are describing I interpret it as the FET is probably on all the time pulled down via the Sig gen. A P channel FET would have the gate driven with respect to the +Ve supply, not the 0V.
To really get help, please draw up a circuit, scan it and post here if you can.

 

Negative side of 50vdc power supply.

Is the negative side of the signal generator also connected to that? It is needed to make a complete circuit for the gate.

 

A circuit really is needed. By what you are describing I interpret it as the FET is probably on all the time pulled down via the Sig gen. A P channel FET would have the gate driven with respect to the +Ve supply, not the 0V.
To really get help, please draw up a circuit, scan it and post here if you can.

Working on Schematic now. Will post shortly.

 

Welcome to AAC!

Post a schematic.

Schematic has been posted.

 

Is the negative side of the signal generator also connected to that? It is needed to make a complete circuit for the gate.

It is. Short bus with muddy wheels. Love it.

Schematic is posted. Thanks for the interest. Any ideas?

 

Schematic is posted. Thanks for the interest. Any ideas?

According to what you've drawn, the MOSFET should always be on.

The MOSFET may have been damaged when you had the offset set to -20V.

 

Hello,

According to what you've drawn, the MOSFET should always be on.

It could even be that the mosfet is broken, due to the to high gate voltage.
Most fets can not work with gate voltage higher than 20 Volts.

Bertus

 

It could even be that the mosfet is broken, due to the to high gate voltage.
Most fets can not work with gate voltage higher than 20 Volts.

Bertus

The data sheet has 20V gate volts so I would agree, the FET is probably toast.
You need something like this...


from https://www.vishay.com/docs/70611/70611.pdf

 

A circuit really is needed. By what you are describing I interpret it as the FET is probably on all the time pulled down via the Sig gen. A P channel FET would have the gate driven with respect to the +Ve supply, not the 0V.
To really get help, please draw up a circuit, scan it and post here if you can.

Schematic has been posted.

Welcome to AAC!

Post a schematic.

According to what you've drawn, the MOSFET should always be on.

The MOSFET may have been damaged when you had the offset set to -20V.

 

How would you change this ckt to make it work? After correcting the ckt, What gate volltage would you suggest for turn on of this MOSFET?

 

How would you change this ckt to make it work? After correcting the ckt, What gate volltage would you suggest for turn on of this MOSFET?

Something like @dendad posted. I'd use a transistor so you don't have to worry about another Vgs:


The zener voltage is chosen to limit maximum Vgs seen by Q1, but high enough to ensure low RDSon. Values for R1 and R2 aren't critical, but R2 needs to be low enough to put the zener past it's knee when Q2 is on. R3 needs to be sized to provide 0.1x the collector current in Q2.

 

Something like @dendad posted. I'd use a transistor so you don't have to worry about another Vgs:
View attachment 137598

The zener voltage is chosen to limit maximum Vgs seen by Q1, but high enough to ensure low RDSon. Values for R1 and R2 aren't critical, but R2 needs to be low enough to put the zener past it's knee when Q2 is on. R3 needs to be sized to provide 0.1x the collector current in Q2.

Thank you. I will build it and let you know.
Dennis Bequette

 

Thank you dl324. Built your ckt on a bread board and replaced Q1. Got no square wave to the gate of Q1. Changed R2 from 10k to 5K. At the junction of R1 and R2 measured 37vdc. Good reversed square wave to the gate of Q1. Still not switching 50vdc on and off to the load (coil). Any suggestions?

Thanks again
Dennis Bequette

 

At the junction of R1 and R2 measured 37vdc. Good reversed square wave to the gate of Q1. Still not switching 50vdc on and off to the load (coil). Any suggestions?

With 50V on the source and 37V on the gate, the drain should be at 50V. It would appear that Q1 is defective.

 

View attachment 137501

Schematic has been posted.

That battery is pushing 2+ Amps through coil (with or without mosfet)...

 

Agreed with dl324. My simulation shows that there is a 27V drop on the Rload with a current of 1.36A through the FET.

If you are not getting any voltage drop across your load, the FET is probably gone.