New to PCB Design and layout. While routing bypass caps, I instinctively give each bypass cap its own via to the ground plane. What would be the disadvantages of having two (or more) bypass caps share the same ground via?

I suspect the consequences are more apparent in high-speed and/or high power designs, but in low-power, low-speed designs, what are the disadvantages of doing this?

 

I'm presuming that this is a digital design. . .
It is the connection of the bypass (decoupling) capacitor to the IC that it is decoupling that is important. The tracks from the capacitor to the Vss and Vcc pins must be as short as possible. What happens between the supply and the IC is less important. It is probably better if the Vss pin and the negative of the decoupling capacitor share the same via, unless that would lengthen the track between them.
Even low speed designs have fast edges - a 74HC device doesn't change state any slower just because it does it less often!

However, it it were small signal analogue, it becomes more important not to have power supply ripple flowing down 0V tracks which are part of the signal.

 

For decoupling I would say its the impedance of the current route at the frequency you have.

So a sine wave at 1 MHz, freq interest is 1 MHz,
for a square wave, its the edge speed , so a 1 MHz square would need to look at up to at least 7 MHz,

The reason its the current route,
is Kirchhoff's law,

as for sharing vias,

Shared via is never going to be as good as a correctly placed individual via,
but its done , with caution.

 

I'd just add. . .
For square waves at lower frequencies, the edges aren't any different to the edges at 1MHz. They just happen less often.

 

I'd just add. . .
For square waves at lower frequencies, the edges aren't any different to the edges at 1MHz. They just happen less often.

@Ian0
you are of course right,
I should l have highlighted that the edge speed set the number of harmonics of the fundamental you need to consider.

For most logic, up to the 7th is enough, but if you have slow logic, then the 3rd is enough, or real fast stuff ,the 11 th is of concern.