Building chronogram for this circuit

Thread Starter

salhi

Joined Nov 29, 2023
86
Why do you think they're not 0? Believe me. You're wrong.
I totally agree with you but i just need extra arguments from you , i really trust you people in these type of stuff i just need extra confirmation on why im wrong, so why they arent zero, because D_2 (input of the second D-FF) is Q_1 which is 1 thus it must change the Q_2 to be 1 too? or is it until the second clock cycle? so both Q_3 and Q_2 will be 0 till the second clock cycle -rising one-?
 

dl324

Joined Mar 30, 2015
18,329
because D_2 (input of the second D-FF) is Q_1 which is 1 thus it must change the Q_2 to be 1 too? or is it until the second clock cycle? so both Q_3 and Q_2 will be 0 till the second clock cycle -rising one-?
You aren't taking propagation delay through the flip flop in to account.

The input to FF1 is 1 on the rising edge of the first clock. It's output won't change to 1 until some time after the rising edge, so the input to FF2 is still 0.

There's absolutely no reason to think that the input to FF3 would have changed to one on the first rising clock.
 

eetech00

Joined Jun 8, 2013
4,705
Hey, so i supposed all Q_i are 0 at t = 0, here is how my first cycle look View attachment 309608
You show the FF's changing state at t1. That's not t0. The clock is low at t0.
So, for initial state, show the state of each FF beginning at t0.

Now, if all FF are initialized at t0 with Q out high (as you wanted), what will happen to Q1 at t1?

Note: it will help if you number each clock half cycle, starting with t0 (zero)
 

Thread Starter

salhi

Joined Nov 29, 2023
86
im basically useless at this point idk what to do, can someone simplify what should i do ? i dont really understand
 

dl324

Joined Mar 30, 2015
18,329
im basically useless at this point idk what to do, can someone simplify what should i do ? i dont really understand
The input to FF1 is HIGH at the first clock. It's still HIGH at the second clock because the output of FF2 hasn't changed yet.
1702158614801.png
Can you follow that?

What is the input of FF1 before the 3rd clock?
 

Thread Starter

salhi

Joined Nov 29, 2023
86
The input to FF1 is HIGH at the first clock. It's still HIGH at the second clock because the output of FF2 hasn't changed yet.
View attachment 309656
Can you follow that?
ah now i understand the propagation time infinite thanks i will follow up and post my answer, its really hard for me to understand the english words meaning while studying this in arabic :/
 

Thread Starter

salhi

Joined Nov 29, 2023
86
But we have a XNOR operation happeing, when FF2's output is high , FF3's output is low thus D must be 0, why is FF1's output still high on rising edge?
 

dl324

Joined Mar 30, 2015
18,329
infinite thanks
Glad the light went on for you.
its really hard for me to understand the english words meaning while studying this in arabic
I figured there was a language barrier when you called it a chronogram. We call them timing diagrams.
But we have a XNOR operation happeing, when FF2's output is high , FF3's output is low thus D must be 0, why is FF1's output still high on rising edge?
The 0 doesn't get clocked in to FF1 until the 3rd clock.
 

Thread Starter

salhi

Joined Nov 29, 2023
86
Glad the light went on for you.
I figured there was a language barrier when you called it a chronogram. We call them timing diagrams.
The 0 doesn't get clocked in to FF1 until the 3rd clock.
thank you so much for being comprehensive, yes my question is why it will turn to be 0 at third 3rd cycle, isnt both Q_2 and Q_3 = 1 then the output of the XNOR will be 1 thus D -input of FF1- will be HIGH too so it wont change?
 

dl324

Joined Mar 30, 2015
18,329
why it will turn to be 0 at third 3rd cycle, isnt both Q_2 and Q_3 = 1 then the output of the XNOR will be 1 thus D -input of FF1- will be HIGH too so it wont change?
Just before the 3rd clock cycle, Q2=1 and Q3=0, so the input to FF1 is 0.
 
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