better now? View attachment 309701

No - the 5th clock is correct, but the 4th clock is now wrong.

 

Ah okey i see the problem, its fixed now?

 

Ah okey i see the problem, its fixed now? View attachment 309703

No. Just stop guessing and work it out.

 

No. Just stop guessing and work it out.

No. Just stop guessing and work it out.

why is it wrong?

 

That's right:
D0=Q1 xnor Q2. Q0 after the clock is D0 before the clock.
before clock- - after clock
Q1 - Q2 - - - - Q0
0 - 0 - ---- 1
0 - 1 ------- 0
1 - 1 -------- 1
1 - 0 -------- 0
0 - 1 ------- 0
Eventually it will repeat.

 

better now ?

 

Yes, now look at all the states that the outputs have gone through and see if any possible state is missing.

 

Yes, now look at all the states that the outputs have gone through and see if any possible state is missing.

Infinite thanks to everyone that helped the stupid me, im grateful to yall!

 

okey this is my final answer View attachment 309691

There's an error at the 5th clock.

What you posted in post #40 is even worse. It looks like what you posted in post #36.
You edited the post after I commented. It's correct now.

You seem to have a problem with propagation delay and setup time.

 

Infinite thanks to everyone that helped the stupid me, im grateful to yall!

You haven't finished yet!

 

It will help if you draw your timing diagram this way.

Y is the output of the NOR gate.

To communicate, you would say, for example, "the first clock is at T1"
or "initialization is at T0", or, "the second clock is at T3"

 

You haven't finished yet!

ow sorry what do i have left to do?!

 

look at all the states that the outputs have gone through and see if any possible state is missing.