Im tasked to plot the chronogram (evolution in-time) of this circuit in terms of \( Q_1, Q_2, Q_3 \) but i dont know the initial conditions of D

Is it really possible to do such task?

 

Im tasked to plot the chronogram (evolution in-time) of this circuit in terms of \( Q_1, Q_2, Q_3 \) but i dont know the initial conditions of D
View attachment 309607
Is it really possible to do such task?

Yes.
True. You don't know D, but for a first attempt assume that your D-latches have a power-on reset (so Q1, Q2 and Q3 all start at zero).
When you have done that, are there any of the eight possible states for which you don't know the next state?
If so, repeat the exercise starting at any states for which you don't know the next state.

 

Im tasked to plot the chronogram (evolution in-time) of this circuit in terms of \( Q_1, Q_2, Q_3 \) but i dont know the initial conditions of D
View attachment 309607
Is it really possible to do such task?

If the clock signal has not begun to run, it is usually low.
If this is true, then what is the state of Q for each FF?

 

i dont know the initial conditions of D

Is it really possible to do such task?

Yes. Just assume whatever initial conditions you want and go through the circuit until a pattern emerges.

 

infinite thanks everyone , so regardless of the state of initial D, the pattern will be periodic whether its 1/0 ?

 

infinite thanks everyone , so regardless of the state of initial D, the pattern will be periodic whether its 1/0 ?

It might. That's for you to determine.

 

It might. That's for you to determine.

Hey, so i supposed all Q_i are 0 at t = 0, here is how my first cycle look

 

Hey, so i supposed all Q_i are 0 at t = 0, here is how my first cycle look View attachment 309608

What makes you think that Q2 and Q3 should go high on the first clock edge?

 

What makes you think that Q2 and Q3 should go high on the first clock edge?

because Q_1 which is their input D is high ?

 

because Q_1 which is their input D is high ?

I thought you were starting with D1,D2 low.

 

Can you have a look at circuit again because i think you are confused about how the inputs of each D-FF

 

Can you have a look at circuit again because i think you are confused about how the inputs of each D-FF

Looks to me as though they are connected Q1-D2, Q2-D3 as in a shift register.

 

Looks to me as though they are connected Q1-D2, Q2-D3 as in a shift register.

yes you are right so where does D1-D2 appear?

 

Study how a D flip flop works. Here's a truth table.

And remember, the DFF you show is a positive clocked device, so it will only change state on the RISING edge of the clock.
Then, go back and re-think your graph in post#7.

 

Hey, so i supposed all Q_i are 0 at t = 0, here is how my first cycle look View attachment 309608

It's wrong. You're not accounting for propagation delay through the flip flops.

 

Study how a D flip flop works. Here's a truth table.
View attachment 309619
And remember, the DFF you show is a positive clocked device, so it will only change state on the RISING edge of the clock.
Then, go back and re-think your graph in post#7.

yea my first cycle is correct, if you think its wrong point it out im pretty sure what i did for the first clock cycle is true

 

yea my first cycle is correct, if you think its wrong point it out im pretty sure what i did for the first clock cycle is true

It's wrong.

 

It's wrong.

okey whats wrong with it?

 

okey whats wrong with it?

Did you read post #15?

On the rising edge of the first clock, the input to FF1 is 1, but the inputs to the other 2 are still 0. You show all outputs changing to 1 at the first clock. That's wrong.

 

Did you read post #15?

On the rising edge of the first clock, the input to FF1 is 1, but the inputs to the other 2 are still 0. You show all outputs changing to 1 at the first clock. That's wrong.

well thats wrong why you think the inputs to the other two D-FF is still zero?