I'm attempting to design an amplifier for a class project. I do not want someone to necessarily solve this for me but just provide some insight. First, the design requirements:


Requirements:
Input impedance > 10k Ohms
output Impedance < 500 Ohms
Gain > 1000 V/V
Vcc = 18 V
Swing = 12V p-p
f_low: 100 Hz
f_high: 1 MHz
load : 2k Ohms

Background:
At first, my partner and I tried just using some capacitor coupled Common emitters followed by an emitter follower. In spice we got the results we designed for but in the lab we had some very strange behaviors. No matter the input to the circuit (magnitude and frequency), we were seeing around a 5 MHz noise signal with about 100 mV on the input and 6 V on the output. We abandoned that design assuming there were some strange factors at play that we don't know how to account for due to all of the coupling and shorting capacitors. Our next design choice was to use a differential pair. This has the advantage (in my mind) of not needing as many coupling capacitors. The strange part about our design is that Vcc is 18 V instead of the normal +/- 9 V that you normally see. I have attached my ltspice schematic which simulates well. When we built the circuit though the first stage differential performed as expected. Then, when we added the second stage we had some clipping so we decided to check our DC bias values. We found that the current was splitting very unevenly on the first diff amp stage which of course causes issues down the line.

Questions:
Is this design just plain dumb?

Is it even possible to design a differential amplifier with discrete components? We checked the Hfe of all the transistors available and matched them as best we could. When I try simulating with different beta values the gain is attenuated slightly but not as much as what we were witnessing.

Any other general advice?

Thanks!

EDIT: those collector resistors should be 30K not 32K.

 

A trivial matter - are you sure you have your "<" & ">" annotations correct in your specification / requirements?
This may well be a project but perhaps should have been posted in the homework section, given the context.

 

If a Mod thinks this should be moved please do so. I wasn't sure exactly but saw projects in the past posted here which were similar to my post. I have fixed the direction of the inequalities in the original post. I can see how that was confusing although when I used the colon I read "Gain: <1000 V/V" as "gain must be greater than 1000..." Sorry about that.

 

So, what is the input voltage peak to peak, and what is the desired gain?

ak

 

MOD NOTE: Moved from The Projects Forum to Homework Help.

You will probably get more attention in this forum.

 

These amplifier designs are very sensitive to parameter mismatch (not just beta) in the transistors.

You can get the basic approach to work if you modify the design to remove the assumption of matched transistors. One way to do this for your current mirrors is to add ballast resistors in the emitters.

The output resistance of the simply current mirror you are using is pretty low. You might try a Wilson or other improved topology.

You also shouldn't put BJT transistors in parallel like you have Q8 and Q9. This is inviting thermal runaway. Again, ballast resistors will address this.

You want to keep the environments seen by the nominally matched transistors as close to identical as possible. This would mean putting an 8kΩ resistor in the collector path of Q5.

You should incorporate circuitry to allow you to tune the gain and offset of the amplifier.

 

Do the specs actually mean the goal is to achieve a gain bandwidth product of 1000 (gain) x 1MHz or 1GHz??
This was (is) a tall order for a monolithic design. Seems ambitious for a discrete BJT design.

 

Thanks for the replies so far. The goal is as described in the requirements. My operating assumption is that if I need at least 1000 V/V gain and an output swing of 12 V p-p then I need a input signal less than or equal to 12 mV. After this project the next one is to modify this one with feedback to achieve a more predictable gain. That is why I started down the differential amplifier route since you basically have already an inverting input. The gain given is assumed to be maximum/midband gain. With f_-3dB at 100 Hz and 1 MHz. Sorry if the convention I used is atypical. It is what I have learned. I have not learned formally anything about ballast resistors in the emitters so I will read up on the subject. Thanks for the advice about parallel transistors as well.

 

Do the specs actually mean the goal is to achieve a gain bandwidth product of 1000 (gain) x 1MHz or 1GHz??
This was (is) a tall order for a monolithic design. Seems ambitious for a discrete BJT design.

It's pretty ambitious, but probably doable. He's got two gain stages so if he can split the gain more or less evenly then he's only talking about a GBWP of 30 MHz or so in each stage.