Hello ,In the attached video at 6:49 they say that the biasing is not alighed and we need to fix it.
I have tried to simulate this effect by building the differential pair with active load in ltspice.

How can I create a common mode missalighnment in the circuit so later I could fix it using feedback?
Thanks.
Ltspice file is attached.

 

update:

I have created a misselighment by changing mosfet W and I connected the V3 as independant source.
How feedback will fix this misselighnment?