

https://forum.allaboutcircuits.com/threads/and-gate-that-uses-trinary-logic.208931/post-2012237I must have missed the explanation of just exactly "trinary logic" is. That "truth table" in post #43 does not make any sense. I have seen a "any two out of three" and gate,implemented with standard CMOS 2-input AND gates and a triple input OR gate.
"Fuzzy Logic" = Marketing ScamYou mean, like fuzzy logic. (Not a concept I’ve ever been greatly impressed by)
As with many things, the fuzzy logic bandwagon attracted a host of wild speculation and promoters along with its share of hypesters and fraudsters. But the underlying concepts of fuzzy logic are well formulated and applications are deep and widespread in many areas for which it is a good match to the problem space, such as control systems, image recognition and feature extraction, medical decision making, complex system modeling, and a variety of others."Fuzzy Logic" = Marketing Scam
Translation: messy conditional logic, written by a sloppy programmer to satisfy the marketing department.
I simulated and it matches all the outputs in the Truth Table. In my table, 0 = LOW, LOW, 1= HIGH, LOW, and 2= HIGH,HIGHI must have missed the explanation of just exactly "trinary logic" is. That "truth table" in post #43 does not make any sense. I have seen a "any two out of three" and gate,implemented with standard CMOS 2-input AND gates and a triple input OR gate.
No, the TS was very specifically asking about trinary (aka, ternary, trivalent, three-valued, etc.) logic -- logic in which each variable can take on exactly one of three possible states.I deduced from the question and the Truth Table that the TS is talking about regular binary AND gate and just messed up the question. If it were Ternary AND gate, the Truth Table had to be 27 rows
I simulated and it matches all the outputs in the Truth Table. In my table, 0 = LOW, LOW, 1= HIGH, LOW, and 2= HIGH,HIGH
correct me what am I missing.
Ok, understood, but which one of the facts on the right column of TS's table does not my design fulfill?No, the TS was very specifically asking about trinary (aka, ternary, trivalent, three-valued, etc.) logic -- logic in which each variable can take on exactly one of three possible states.
The basic gate definitions are still between two operands. Just like addition and multiplication are defined between two operands, regardless of how many (including an infinite number) of values those operands can take on.
Your design is not implementing trinary logic at all!Ok, understood, but which one of the facts on the right column of TS's table does not my design fulfill?
1 LED translates to 1, two LED translates to 2, and 0 LED translates to 0, which corresponds to the states in columns A&B.
Again, gate A LOW,LOW = 0 LOW,HIGH =1 and HIGH, HIGH =2. The same applies to gate B. Where is the flaw in the logic?
I am not aware of any dedicated trinary chip. Could you give a part number please?Your design is not implementing trinary logic at all!
You are, at best, emulating it using multiple binary-valued variables to represent a single trinary variable.
You tell me what you expect from the design to do for you, and I will tweak it or come up with something else. But for now, I am not sure what "2" is supposed to do? Would a 3-state rotary switch represent those 3 states :0,1,2 ?While it can be made to function on paper , it will probably be a challenge to produce the function in actual electronic hardware. AND I wonder if the TS has considered the fuctionality of a trinary FlipFlop? OR is this added logic scheme restricted to AND gate logic?? Please show us how it works with the rest of logic functions.
The TS wasn't asking about parts that they could purchase today. They were asking about how ternary logic could be implemented, in particular using MOSFETs.I am not aware of any dedicated trinary chip. Could you give a part number please?
The irony: the cheapest SSDs are those stacked up ones.......... This is one of the keys to getting huge memory densities in SSDs. I think most of the the stuff today is not using 3 states per cell, but 8- or even 16-states per cell and 32-level storage is in the demonstration stage and will probably hit the market in the not-too-distant future.......