While it can be made to function on paper , it will probably be a challenge to produce the function in actual electronic hardware. AND I wonder if the TS has considered the fuctionality of a trinary FlipFlop? OR is this added logic scheme restricted to AND gate logic?? Please show us how it works with the rest of logic functions.

As with Boolean logic, you start with what your levels mean and then define how they can be combined using various operators.

In the most common ternary logic system, K3, the three values are (as mentioned above) F < U < T. Unlike the Boolean True and False, which have no intrinsic order, the values in K3 (and most multi-level logic systems) are ordered and then plays a role in understanding the operator definitions.

The Negation (NEG) operator flips the values, leaving U unchanged.

This can be implemented in CMOS using transistors whose thresholds are controlled such that with a voltage near half the supply voltage is applied, the output voltage is near half the supply voltage. In binary CMOS, this is bad juju, because it results in an undefined output at best, and potentially destructive shoot-through currents at worst. But this is not the case in ternary logic because the transistors are designed to implement ternary logic, not binary logic.

What is commonly called the AND and OR operators (and I think that this is unfortunate, because it naturally leads people into trying to interpret these functions in terms of the 'and' and 'or' notions of everyday language and the binary-logic interpretations that arose from it) should properly be (and in some systems are) called MIN and MAX, respectively.

This is one of the reasons that mathematical logicians don't like to use AND and OR, but rather "conjunction" (using the '^' symbol) and 'disjunction' (using the 'v' symbol).

The MIN function yields the minimum value of any of its inputs, while the MAX function returns the maximum value of any of its inputs. These work for N-value logic and, in the case of 2-value logic (i.e., Boolean logic) reduce to our familiar AND and OR.

For any other functions, you simply define them using the generalization of the NOT, AND, and OR definitions in binary logic to use NEG, MIN, MAX.

For example, implication (IMP) in binary has the form:

A -> B = AND(NOT(A), AND B)

In ternary logic, it has the same functional definition

A -> B = MAX(NEG(A), B)

XOR is defined, in binary, as

XOR (A, B) = OR( AND( NOT(A), B ), AND( A, NOT(B) ) )

In multi-level logic, it is defined as

XOR (A, B) = MAX( MIN( NEG(A), B ), MIN( A, NEG(B) ) )

If you slog through writing the truth table, what you will discover is that it reduced to the Boolean XOR function when both inputs take on Boolean values.

As for the Flip Flop, I don't know what the issue is. The basic notion of a Flip Flop is the D-type flip flop which stores the value at it's input, which is all that a ternary flip flop would be required to do.

 

The irony: the cheapest SSDs are those stacked up ones

That's a major factor in why it's used.

One of the downsides is that it is not as robust and has a higher error rate, precisely because the margins between valid levels are reduced. So if you want the maximum reliability, you use single-level cells, which means that it requires a lot more cells (each of which is actually cheaper to manufacture, because the tolerances are looser), but you need more of them, and hence more semiconductor area, which is the big determiner in the final cost of commodity devices (coupled with yield, of course).

 

That's a major factor in why it's used.

One of the downsides is that it is not as robust and has a higher error rate, precisely because the margins between valid levels are reduced. So if you want the maximum reliability, you use single-level cells, which means that it requires a lot more cells (each of which is actually cheaper to manufacture, because the tolerances are looser), but you need more of them, and hence more semiconductor area, which is the big determiner in the final cost of commodity devices (coupled with yield, of course).

You know your stuff no doubt. But I am sure you know as well that the multi-level NANDs were not a challenge to overcome. It was "Whether I should do it or not" that was the impediment. I read somewhere years ago that we were reaching the limits of how compact the ICs can be and that it was not a technological barrier, rather, the laws of physics pose thse limits. You know better, but what I remember is that it had to do with electrons bouncing to the adjacent cells that were not supposed to and cause data corruption.
The point being, how smaller can I make is no longer the issue. We have passed that point. The issue at hand is efficiency in the era of energy crisis. Surly they can make a cellphone the size of a wristwatch, but you still prefer a minimum 6" screen!

 

OK, I see that there is more ternary logic hardware around than I was aware of. Certainly the programs using any multiple-state logic will be a bit different. THERE LIES the potential for problems: Binary logic is more common and a lot more people are able to understand it and make it work. The lack of familiarity with other logic makes the application less desireable because fewer folks can quickly deal with it. Sort of like the "BIG TRUCK" with the 12 speed transmission: Not everybody can drive it.