analog IC design in the submicron technology (12nm<L<180nm)

Thread Starter

TarikElec

Joined Oct 17, 2019
147
Hi everyone,
I come accross to learn to design in submicron wiht cadence virtuoso with the process technology (12nm<L<180nm). as I am a guy who likes to do hand calculation and estimate before simulation, I got struck how the square law model does not provide any resulte that make sense with the specifications and calculations.Ifound out nothing is constant like, Lambda, Vth0, Kn',... and everything is changing with L. Vds, Vgs, ID,...
Q1:How can we even design anything if everything is variable by over 100%?
I saw that the Id/gm methodology ,but to be honest , I like more hands on analysis.
My second question: Q2: if for example L=40nm is a submicron technology, ifmake L=1um, will the square law applies?
 
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